Testing semiconductor furnaces for heavy metal contamination

Details Testing semiconductor furnaces for heavy metal contamination Testing semiconductor furnaces for heavy metal contamination

1980-11-14

1983-12-13

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

73 23, 324 715, 357 89, 422 98, G01N 2700, G01N 2712, G01N 3122

Patent

active

044207220

ABSTRACT:
A technique for testing for heavy metal contamination in semiconductor processing furnaces includes use of a chip having a plurality of PN- junctions, at least one of which is completely isolated from the sides of the chip. The chip is manufactured to exhibit a high reverse recovery time and this can be conveniently accomplished by a combination of a gettering layer to getter the heavy metal atoms away from the junction and by never raising the temperature of the chip above 800.degree. C. after the gettering layer is provided.
In use, the chip is fed through a furnace either with or, preferably before the wafers being processed, which is operating at the conditions under which semiconductor devices are to be processed. After the chip is removed from the furnace, its reverse recovery time is measured and compared to its initial reverse recovery time to determine if it has decreased.

REFERENCES:
patent: 2827436 (1958-03-01), Bemski
patent: 2965842 (1960-12-01), Jacobson
patent: 3865550 (1975-02-01), Bott et al.
patent: 3879985 (1975-04-01), Maslen
patent: 4135951 (1979-01-01), Stone
patent: 4216038 (1980-08-01), Nishizawa et al.
patent: 4239558 (1980-12-01), Morishita et al.
patent: 4283236 (1981-08-01), Sirsi

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