Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-06-05
2003-09-16
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S017000
Reexamination Certificate
active
06620638
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor processing technology and, in particular, concerns methods of testing multi-chip electronic modules.
2. Description of the Related Art
Semiconductor manufacturers continually strive to increase the packaging density of integrated circuit chips, which has led to the development of high-density electronic packaging modules such as three-dimensional multi-chip structures. Multi-chip structures typically comprise a plurality of integrated circuit chips that are adhered together in a stack so as to reduce the amount of space that the chips occupy inside a system. Typically, each chip in the stack has a plurality of conductive input/output contacts that are exposed on at least one lateral surface of the chip. The exposed contacts provide conductive interconnection between the chips in the stack and external circuitry.
As a result of the increased device density of VLSI (Very-Large-Scale Integration) and ULSI (Ultra-Large-Scale Integration) integrated circuitry, wiring interconnective metallurgy between integrated circuit devices has become increasingly more complex. A higher packaging density likely requires an increase in the number of conductors, which likely reduces the space between adjacent conductors. Unfortunately, such dimensional reductions tend to increase the capacitance between adjacent conductors, thereby possibly increasing signal propagation delays and signal cross-talk. The limitations brought about by capacitive coupling between adjacent conductors has become a significant impediment to achieving higher wiring density.
The capacitive coupling effect is particularly apparent in high-density electronic packaging modules, such as three-dimensional multi-chip structures. In some multi-chip structures, the conductive leads on the integrated circuit chips are closely spaced, and adjacent leads may sometimes be separated by less than 1 micron. Consequently, reducing the distance between adjacent leads may adversely impact the functionality of the multi-chip structure due to an increase in the capacitive load between adjacent conductors. In addition, stacking the chips in close proximity to one another as required in multi-chip structures may also increase the capacitive coupling effect between conductors of adjacent chips.
Many integrated circuit chip designers have tried to address the problem of increased capacitive coupling between adjacent conductors by utilizing insulative materials that have lower dielectric constants than conventional dielectrics such as silicon-dioxide (SiO
2
), which has a dielectric constant of about 4.5. In some cases, polymers, such as polyimides, which have a dielectric constant of about 2.8-3.5, have been used in place of SiO
2
. However, the polyimides provide limited improvement for the capacitive coupling problem and, therefore, do not provide a significant advantage in use.
Alternatively, interconnects incorporating an air bridge structure have also been developed and are described in prior art references such as U.S. Pat. No. 5,891,797 to Farrar. Air bridge structures generally comprise suspended conductors that are surrounded by an air gap instead of the more conventional insulators. For example, U.S. Pat. No. 5,324,683 to Fitch et al. describes the formation of an air bridge structure in an integrated circuit by removing all or a portion of the dielectric layer between conductors so that the conductors are surrounded and insulated by an air gap. Air has a dielectric constant of approximately 1.0, which is substantially less than the dielectric constants of conventionally used insulators such as SiO
2
or various polyimides. As such, the air-gap insulator provides some improvement for the capacitive coupling effect associated with the increased wiring density of integrated circuit chips.
Although air bridge structures facilitate the development of integrated circuits with higher wiring density, the use of air bridge structures introduces new manufacturing challenges such as protecting the suspended air bridge conductors from being damaged during fabrication. To address this concern, a temporary support material as disclosed in Applicant's co-pending U.S. patent application Ser. No. 09/945,024, entitled MULTI-CHIP ELECTRONIC PACKAGE AND COOLING SYSTEM, which is hereby incorporated by reference in its entirety, can be used to stabilize and support the air bridges during fabrication. The temporary support material can be positioned beneath suspended air bridge conductors during manufacturing to provide rigidity to the conductors and subsequently removed when the chip stack assembly is complete. Disadvantageously, however, the temporary support material can impose certain constraints on in-process testing of the individual chip components and sub-assemblies.
In typical chip production, chips are tested at one or more points through a series of process steps with final functional testing of the individual chips being done prior to packaging. At many of these test points, chips such as memory chips are typically exercised at its rated speed and logic chips are tested for their speed and logic functions. Chips that pass the tests are usually packaged and subject to additional testing including margin tests for memory chips and more extensive functional tests for logic chips along with speed testing and sorting. With the higher speed sorts, generally, receiving a premium price in the market place. In some cases, if the chips are running at a relatively high yield, the final functional testing for chips may be delayed until after packaging, thus saving one testing cycle. For example, in the construction of large processors, memory chips with relatively high yield may be first assembled onto cards and these cards are then tested upon assembly. Additionally, a final system test is typically performed upon completion of assembling the entire system. Thus, the various testing steps allow defective chips to be detected and repaired or discarded at each step of the chip fabrication and assembly process.
However, the presence of the temporary support material in multi-chip structures may significantly increase the capacitive load on individual circuit elements thereby temporarily altering various functional properties of the integrated circuit devices. This temporary change in device characteristics caused by the support material makes it difficult to obtain accurate in-process device test results. Consequently, defective devices cannot be distinguished from the properly functioning ones during fabrication.
Hence, from the foregoing, it will be appreciated that there is a need for a method of performing accurate in-process testing of integrated circuit chips when the device properties are temporarily altered during the fabrication process. To this end, there is a particular need for a method of performing accurate in-process testing of a multi-chip electronic module comprising air bridge structures supported by a temporary material that affects the capacitive load of the circuit elements during fabrication.
SUMMARY OF THE INVENTION
In one aspect, the preferred embodiments of the present invention provide a method of manufacturing an integrated circuit chip, incorporating a novel in-process test sequence. The method comprises first forming a plurality of devices on a semiconductor substrate and then testing the device properties to determine if the devices are functional. Preferably, the testing is performed on special Kerf sites formed on the substrate. The method further comprises forming a plurality of conductors wherein at least some of the conductors are air bridge structures supported by a temporary member that may alter the device properties. In one embodiment, after formation of the conductors, the chip is subject to a chip metallurgy test performed on special Kerf test sites to determine whether the conductors are properly formed. The structures in the Kerf may include both active devices along with conductive structures which enable the t
Knobbe Martens Olson & Bear LLP
Luk Olivia
Niebling John F.
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