Testing of logic arrays

Details Testing of logic arrays Testing of logic arrays

1981-06-04

1984-03-06

Smith, Jerry

Excavating

371 8, 371 15, G06F 1100

Patent

active

044358059

ABSTRACT:
A logic array includes a matrix of logical elements located at the intersections of a plurality of input and output lines. Due to the nature of the array structure, more than one output line may be activated by a given digital bit pattern placed on the input lines. In testing the array, the lack of a one-to-one correspondence makes it difficult to determine if the personalization associated with a given output line is proper.
The output line interference problem is solved by providing a deletion control line which may be selectively connected to any combination of output lines to thereby disable the connected output lines. Thus, a given output line may be personalized, tested and the disabled, to preclude interference between the tested output line and the remainder of the lines to be tested. Moreover, since the logic array is tested one line at a time, provision can be made for substituting spare output lines for defective output lines, thereby rendering a defective array usable.

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