Testing method for a reading operation in a non volatile memory

Details Testing method for a reading operation in a non volatile memory Testing method for a reading operation in a non volatile memory

2002-02-05

2004-02-17

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185200, C365S185240

Reexamination Certificate

active

06693829

ABSTRACT:

FIELD OF THE APPLICATION
This invention relates to a testing method for a reading operation in a memory device.
PRIOR ART
As is well known, it is common for so-called “on-chip” systems to have two different supply-voltage references.
In particular, systems intended for automotive use usually have a first or external supply-voltage reference of about 5V±10%, hereinafter designated VDDEXT, and a second or internal supply-voltage reference, hereinafter designated VREG, which is a regulated voltage.
In general, the second regulated voltage reference VREG is derived from the first voltage reference VDDEXT as the low-voltage output of a voltage regulator, which is usually integrated into the system.
Non-volatile memories, in particular flash memories, which are also integrated into the system, use the internal regulated voltage reference VREG for their supply reference, whose value usually approximates 2V in the instance of 0.18 &mgr;m technologies.
Such flash memories sometime also use the external voltage reference VDDEXT in the voltage booster circuits with which they are usually equipped.
In automotive applications, reliable system performance is of primary concern, especially at power-up or power drop of either of the external and internal supply voltage references, VDDEXT and VREG.
In fact, outside the power-supply range specified for the memory (1.8V±10% for a flash memory), the correctness of any data read in the memory cannot be ensured, and thus the proper operating of the system is a consequence of such reading.
Accordingly, this is a matter of preventing the Flash memory from being read outside said safe range.
Particularly with automotive applications, the specifications for normal operation of the system (such as a minimum power-supply reference level, or a pre-set duration of the read-voltage ramp, etc.) cannot be ensured in case of a breakdown of the vehicle comprising such a system. There is a risk that the application could fail, thus obtaining no predetermined results, because the data could be read incorrect.
The importance of reliability in data reading is highlighted by the control of crash airbags on a vehicle: here the risk would be that an incorrect data reading would activate them at an improper time.
To avoid incorrect data reading, and malfunctioning of the whole system, it has been common practice to arrange for an external device to enable reading in a flash memory only if conditions are right. In particular, such an external device comprises essentially low-voltage detectors, which are connected to the-external and internal supply-voltage references of the flash memory.
In practice, it is difficult to design reliable detectors having a threshold value which lies very close to the minimum value in the supply-voltage range specified for a flash memory (normally 1.6V±50 mV), and being stable through the temperature range (−40° C. to 125° C.) that prevails in an automotive environment.
Thus, it is difficult to provide circuit devices operative to enable reading in a flash memory only when the information is sure to be read correctly, that is when the voltage references are within a pre-set range.
Consequently, there is a need for a technique for testing a reading operation in a non-volatile memory for correctness and that overcomes the limitations of the prior art.
SUMMARY OF THE INVENTION
One embodiment of the present invention includes a method for:
providing first and second memory cells having predetermined threshold values;
pre-programming a logic value in the first and second cells;
performing a reading operation in the first and second cells;
comparing the values read with the expected logic contents of the cells;
based upon the outcome of the above comparison, deciding whether to continue reading from the memory device that contains the first and second cells.
Another embodiment of the invention includes a memory device that implements this testing method.
Further features and advantages of the invention will be apparent from the following detailed description thereof, to be read in conjunction with the accompanying drawings, in which:


REFERENCES:
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patent: 5386388 (1995-01-01), Atwood et al.
patent: 5539690 (1996-07-01), Talreja et al.
patent: 6219282 (2001-04-01), Tanaka
patent: 2001 022650 (2001-01-01), None

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