1995-05-04
1996-05-28
Beausoliel, Jr., Robert W.
39518318, 39518305, G06F 1100
Patent
active
055220380
ABSTRACT:
A system for validating mapped signal generation permits identifying deficiencies in dynamic random access memory testing. As an example application of mapped signals consider memory testing. Memory tests such as stripe and checkerboard pattern tests frequently involve topological maps in order to permit use of the same memory test system and test program on memory devices and systems having different characteristics. An effective memory test exercises a memory cell by storing data therein which is of opposite physical polarity to data stored in physically adjacent cells. Topological maps account for variation in polarity of stored data depending on the address of a cell and variation due to the physical layout of cells which may not necessarily place consecutively addressed cells in physical proximity. A fixture for dynamic random access memory testing according to the present invention includes a battery, a signal multiplexer, and mode switching circuitry. Test methods using such a fixture allow correlation of the performance of a second tester to the performance of a first tester. According to a test method of the present invention, a first tester writes a test pattern into a memory device mounted on a fixture, the memory device is moved to the second tester, and an evaluation is made based on a pattern read-back operation conducted on the second tester. The read-back pattern is compared to the pattern preserved in the memory device by operation of circuitry in a test fixture of the present invention.
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Duesman Kevin G.
Lindsay R. Brent
Beausoliel, Jr. Robert W.
Micro)n Technology, Inc.
Palys Joseph E.
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