Testing macros embedded in LSI chips

Details Testing macros embedded in LSI chips Testing macros embedded in LSI chips

1978-10-16

1980-09-30

Atkinson, Charles E.

Excavating

324 73R, 371 25, G01R 3128, G06F 1100

Patent

active

042259576

ABSTRACT:
Testing combinatorial logic sectioned into macros. The macros perform functions some of which are linear, such as busses, and some of which are non-linear such as PLAs, with the macros being connected so that the total chip can be tested by testing each macro individually to thereby make it unnecessary to model the totality of the macros collectively in terms of primitive logic.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 3961251 (1876-06-01), Hurley et al.
patent: 3961252 (1976-06-01), Eichelberger
patent: 3961254 (1976-06-01), Cavaliere et al.
patent: 4051353 (1977-09-01), Lee
patent: 4058767 (1977-11-01), Muehldorf et al.
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4074851 (1978-02-01), Eichelberger et al.
Muehldorf and Williams, Embedded Macro Test Pattern Generation, IBM Tech. Disclosure Bulletin, vol. 20, No. 1, Jun. 1977, pp. 197-199.
Abramson et al., Reduced Fault Testing for Array Logic Board, IBM Tech. Disclosure Bulletin, vol. 21, No. 7, Dec. 1978, pp. 2678-2679.

Affiliated with

Also associated with

Rating

Testing macros embedded in LSI chips does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testing macros embedded in LSI chips, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing macros embedded in LSI chips will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1173351