Testing integrated circuits provided on a carrier

Details Testing integrated circuits provided on a carrier Testing integrated circuits provided on a carrier

1989-10-10

1995-07-04

Baker, Stephen M.

Excavating

371 225, G01R 3128

Patent

active

054307350

ABSTRACT:
A method for testing integrated circuits provided on a carrier. The circuits include a series input (22) and a series output (24) for test and result patterns. A mode control register (30) receives a mode control signal train via the serial input. Under the control of said mode control signal train the serial input and output can be shortcircuited to each other, or further registers (32, 34, 36) can be selectively filled and emptied. In this manner, both the interior of the integrated circuit and respective interconnection functions can easily be tested by a universal protocol. Integrated circuits and the carrier only require minor extension/adaptations.

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VHSIC Phase 2 Interoperability Standards ETM-Bus Specification, Dec. 31, 1985, Version 1.0; copyright 1985 IBM Honeywell TRW.
VHSIC Phase 2 Interoperability Standards ETM-Bus Specification, Aug. 31, 1986, Version 1.1, copyright 1985 IBM Honeywell TRW.
Avra, L., "A VHSIC ETM-Bus-Compatible Test and Maintenance Interface", 1987 Int'l. Test Conf., pp. 964-971.
Griffin, K., "VHSIC Phase 2 Test Requirements for the Depot", AUTOTESTCON 1989, pp. 289-294.
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Search by DTIC for documents on VHSIC.

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