Testing integrated circuit pad input and output structures

Details Testing integrated circuit pad input and output structures Testing integrated circuit pad input and output structures

1991-07-02

1994-11-29

Beausoliel, Jr., Robert W.

Excavating

371 24, 371 251, 3241581, H04B 1700

Patent

active

053696450

ABSTRACT:
Digital integrated circuit testable input/output pad logic includes modified output driver logic and a latch for storing a test bit provided externally at the I/O pad terminal. The output driver logic selects either the normal pad output signal (O) for output during normal operation, or the stored test bit (S) or its complement (S') for output during a test operation. The output driver logic and latch are controlled by control logic signals (DP,SP,NDN,LS,NLS,NSN) derived from common tri-state (NTR) and latch (NTM) test signals provided externally at dedicated test pins (NTR,NTM). The control logic signals are provided over a bus to all similar testable I/O pads for testing all testable I/O pads within the IC under control of the two test signals.

REFERENCES:
patent: 4485472 (1984-11-01), Sproull et al.
patent: 4703484 (1987-10-01), Rolfe et al.
patent: 5003204 (1991-03-01), Cushing et al.
patent: 5155733 (1992-10-01), Blecha, Jr.

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