Testing digital electronic circuits

Details Testing digital electronic circuits Testing digital electronic circuits

1983-10-26

1986-01-21

Atkinson, Charles E.

Excavating

324 73R, G01R 3128

Patent

active

045661049

ABSTRACT:
A large-scale integrated circuit chip includes a plurality of bistables connected to combinational logic. In a diagnostic mode, the bistables are operated as a serial shift register, allowing test data to be shifted through the chip between diagnostic input and output pins (LPIN,LPOUT). In a chip test mode, the serial shift register is split into a number of shift register portions, each of which is connected between a separate pair of input and output pins. This allows test data to be shifted through all the shift register portions in parallel so as to speed up testing of the chip.

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Tsui, In-Situ Testability Design (IST-D)-A New Approach for Testing High-Speed LSI/VLSI Logic, Proc. of the IEEE, vol. 70, No. 1, Jan. 1982, pp. 59-78.
Fanatsu et al., Designing Digital Circuits with Easily Testable Consideration, 1978 Semiconductor Test Conference, Cherry Hill, N.J., 31 Oct.-2 Nov. 1978, pp. 98-102.
Williams, Testing of LSI Logic Circuits Containing Imbedded Shift Arrays, IBM Tech. Discl. Bulletin, vol. 20, No. 10, Mar. 1978, pp. 4021-4022.
Kurtzenburg and Roth, "Partitioning for Testing", IBM Technical Disclosure Bulletin, vol. 25, No. 3B, Aug. 1982, pp. 1733-1734.

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