Optics: eye examining – vision testing and correcting – Spectacles and eyeglasses – With antiglare or shading
Reexamination Certificate
2001-08-14
2003-04-22
Niebling, John F. (Department: 2812)
Optics: eye examining, vision testing and correcting
Spectacles and eyeglasses
With antiglare or shading
Reexamination Certificate
active
06550911
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to semiconductor devices, and more particularly to a structure for and a method of supplying power to the dies on a wafer during wafer testing.
As the complexity of semiconductor devices increases, the amount of time required to properly test these devices also increases. For example, with advancing technology, memory devices increase in density and complexity, and the time to properly test all memory cells and the different functions of these memory devices increases significantly. Given the high volume production of some memory devices and other semiconductor devices, the increase in test time and the corresponding testing cost can significantly increase the cost of the product.
Conventional testing of semiconductor devices includes a number of steps which can broadly be grouped into two: (i) wafer sort, for identifying defective dies at wafer level, and (ii) final test, for identifying defective packaged devices. While at final test multiple packaged devices, e.g.,
8
,
16
, or
64
, can be tested simultaneously, at wafer sort, the dies are tested sequentially. Thus, wafer sort time is significantly longer than final test time.
Conventionally, each die on a wafer is tested by placing a probe card connected to a test equipment on the contact pads of the die. The probe card supplies the proper power supply levels and control signals to the contact pads on the die. The electrical contact between the probe card and the die contact pads is maintained until the testing of the die is completed. The probe card is then moved to the next die, and the same steps are repeated. Because the number of dies on a wafer is increasing rapidly due to the increasing wafer size and the decreasing processing feature sizes, this method of sequential testing of the dies on a wafer can significantly increase the wafer sort time and cost. Thus, reducing the wafer sort time is desirable.
SUMMARY OF THE INVENTION
In accordance with the present invention, wafer testing time is significantly reduced by initiating built-in self test (BIST) operation in each of the dies of the wafer in such way that the BIST operation in a number of the dies overlap.
In one embodiment, a plurality of dies on a wafer are tested as follows. The wafer is placed in a tester. A built-in self test (BIST) operation is initiated in a first die. Another BIST operation is initiated in a second die after initiating the BIST operation in the first die such that the BIST operation in the first die and the BIST operation in the second die overlap.
In another embodiment, each of the plurality of dies has a circuit, and upon initiating each of the BIST operations, power is supplied to the circuit, designed-in test operations are performed, data reflecting the results of the designed-in test operations are stored in a register, and power is removed from the circuit.
In another embodiment, the data stored in the register of each die is evaluated upon completion of the BIST operations to determine the action to be taken with respect to each die.
REFERENCES:
patent: 5404099 (1995-04-01), Sahara
patent: 6196677 (2001-03-01), Spano
Niebling John F.
Stevenson Andre' C.
LandOfFree
Testing dies on a semiconductor wafer in a sequential and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Testing dies on a semiconductor wafer in a sequential and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing dies on a semiconductor wafer in a sequential and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3098450