Testing device for concurrently testing a plurality of semicondu

Details Testing device for concurrently testing a plurality of semicondu Testing device for concurrently testing a plurality of semicondu

1994-12-01

1997-02-18

Beausoliel, Jr., Robert W.

Excavating

371 211, 371 27, 371 213, G06F 702

Patent

active

056047568

DESCRIPTION:

BRIEF SUMMARY
TECHNICAL FIELD

The present invention relates to equipment for testing a semiconductor memory such as a DRAM (dynamic random access memory), a SRAM (static random access memory), a flash memory or the like, and more particularly, but not exclusively, to such memory testing equipment which is capable of concurrently testing a plurality of semiconductor flash memories as well as ordinary DRAMs and SRAMs.
FIG. 1 shows the basic construction of conventional semiconductor memory testing equipment. The semiconductor memory testing equipment comprises a timing generator 10, a pattern Generator 2, a waveform shaper 3, drivers DR, a logical comparison part 40 and a fail analysis memory 5 and carries out a test on a memory under test MUT. When the testing equipment is used only to make a pass/fail test of a semiconductor memory, however, there are cases where the fail analysis memory 5 is not used.
The pattern generator 2 responds to a reference clock CK from the timing generator 10 to output an address signal ADRS, a test data signal TPD and a control signal CS which are fed to the memory under test MUT. These signals are each shaped by the waveform shaper 3 into logical form necessary for test and rendered by the driver DR into a drive waveform of an actually required voltage, thereafter being applied to the memory MUT.
The test data signal TPD is written into or read out of the memory MUT under the control of the control signal CS. A test data signal RD read out of the memory MUT is provided to the logical comparison part 40, which compares expected data ED from the pattern generator 2 and the read-out test data RD to conduct a pass/fail test on the memory MUT depending upon whether they match or not.
When they do not match, the logical comparison part 40 applies a fail signal to the fail analysis memory 5 and the fail information is stored in that one of memory cells in the fail analysis memory 5 which is specified by the address signal ADRS from the pattern generator 2. After completion of the test, the stored contents of the fail analysis memory 5 are analyzed.
With a view to improving the test efficiency, it is a general practice in the actual line to do simultaneous, parallel testing of a plurality of memories MUT.sub.1 through MUT.sub.n.
Now, a description will be given of the flash memory.
In recent years, the flash memory has attracted attention as a non-volatile memory which is large-capacity and rewritable a number of times. Because of a specific structure of the flash memory, data cannot always be successfully written in each address by one write operation; hence, the write operation usually needs to be repeated a plurality of times. The number of times the write operation needs to be carried out until the write can be effected successfully varies with the kind of the memory MUT and even in the same kind of memory MUT, it varies from address to address. In its data write test, the flash memory is judged as non-defective when data can be written into all desired memory cells within a prescribed number of times the write operation is carried out. The same is true of a data erase test; the memory is judged as non-defective when data can be erased from all desired memory cells within a prescribed number of times the erase operation is carried out.
FIG. 2 shows the construction of the logical comparison part 40. The logical comparison part 40 includes a plurality of logic comparators 4.sub.1 through 4.sub.n which are each supplied with the read-out data RD from one of the memories MUT.sub.1 through MUT.sub.n and compare it with the expected data ED, and an all-pass detector 43 formed by a NOR gate. In this example, the logic comparators 4.sub.1 through 4.sub.n each compare the result of an analog logical decision at the timing of the strobe of input data with the expected data ED by a mismatch detecting circuit 4X formed by an XOR gate; the logic comparator outputs a "0" or "1" depending upon whether they match (PASS) or not (FAIL). FAIL/PASS STATUS data (hereinafter referred to simply as F/P data), which

REFERENCES:
patent: 5062109 (1991-10-01), Ohshima et al.
patent: 5214654 (1993-05-01), Oosawa
patent: 5410687 (1995-04-01), Fujisaki et al.

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