Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2000-07-21
2004-07-20
Hoff, Marc S. (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C324S523000
Reexamination Certificate
active
06766266
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to a testing device and testing method for a semiconductor integrated circuit (e.g., a LCD driver IC, etc.) that incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via the associated output terminals, and particularly relates to a testing device and testing method which can examine the output voltages from the D/A converters, very quickly with high accuracy.
(2) Description of the Prior Art
With the development of LCD panels into a high precision configuration, LCD driver LSIs incorporated in LCD panels have become developed to deal with a greater number of outputs and a greater number of tones. For such tonal display, each output circuit in the LCD driver LSI incorporates its own D/A converter to output a tonal voltage. For example, a 6 bit D/A converter can display 64 levels of tones while a 8 bit D/A converter can display 256 levels of tones.
Upon the test for such a LCD driver LSI, it is checked if all the tonal voltage levels output from individual D/A converters fall within respective correct ranges and if the values of a tonal voltage level for all D/A converters meet the predetermined uniformity.
FIG. 1
is a conceptual view illustrating a conventional testing method by using a test example of an LCD driver LSI
51
incorporating ‘m’ output D/A converters
52
each having ‘n’ tonal levels.
A semiconductor testing device (tester) is used to supply an input signal to an LCD driver LSI
51
so that each D/A converter
52
outputs a voltage level corresponding to the first tonal level. The voltage levels corresponding to the first tonal level are output from associated output terminals (Y
1
, . . . , Ym) of LCD driver LSI
51
and input to input channels (
1
ch, . . . , mch) of tester
53
. In tester
53
, matrix switches
54
are sequentially turned on and off so that the outputs corresponding to the first tonal level are sequentially measured from the first output to the m-th output, one by one, using a high accuracy analog voltage measuring device
55
incorporated in the tester. The measured results are sequentially stored in an incorporated data memory
56
. This process is repeated for ‘n’ tonal levels until all pieces of data relating to all the outputs (m outputs) for all tonal levels (n levels) can be stored into memory
56
. As a result, m×n pieces of data will be stored into memory
56
. The data stored in this memory
56
is subjected to a series of logical and arithmetical operations through an unillustrated processing unit incorporated in tester
53
so as to check each tonal voltage value of each output and the uniformity of each tonal voltage level between all the outputs.
In the testing of an LCD driver LSI
51
, with the development towards a greater number of outputs and a greater number of tones, the amount of data to be picked up and the time required for data processing increase, so that the testing time increases sharply. Further, increasing the number of tonal levels requires a greater precision for measuring the voltage of each tonal level, needing longer testing time and also an expensive semiconductor testing device incorporating a high precision voltage measuring device.
As stated above, as LCD driver LSIs have become developed to deal with a greater number of outputs and a greater number of tones, the conventional testing method needs a much longer testing time and also needs an expensive semiconductor testing device incorporating a high precision voltage measuring device. Thus, the test cost is increasing more and more.
As a conventional semiconductor testing device to solve the above problems, Japanese Patent Application Laid-Open Hei 9 No.312569 has proposed a semiconductor testing device.
FIG. 2
is a block diagram showing the configuration of the semiconductor testing device disclosed in Japanese Patent Application Laid-Open Hei 9 No.312569.
The D/A converter testing device of this disclosure includes: a digital signal generator
60
for generating n-bit digital data; a clock generator
61
; a D/A converter DUT
62
of a device under test which receives the data from digital signal generator
60
and a clock signal from clock generator
61
and outputs an analog signal Vg; a reference (REF) D/A converter
63
which receives the data branched from digital signal generator
60
and the clock signal branched from clock generator
61
and outputs a reference voltage Vref; a differential amplifier
64
receiving the output from D/A converter DUT
62
of the device under test at its one input and the output from reference D/A converter
63
at the other input to effect differential amplification; and a dual comparator
65
which receives the differential amplification output from differential amplifier
64
and checks if the signal in question falls in the allowable range between the upper and lower boundaries. With the above configuration, it is possible to provide a D/A converter testing device that provides a high throughput.
However, the semiconductor testing device (D/A converter testing device) disclosed in Japanese Patent Application Laid-Open Hei 9 No.312569 has suffered from the following difficulties. In the D/A converter testing device shown by Japanese Patent Application Laid-Open Hei 9 No.312569, since the same signals are input to both D/A converter DUT
62
of the device under test and reference D/A converter
63
, it is necessary to use a non-defective D/A converter of the device under test for reference D/A converter
63
. This is because the number of terminals is different depending upon the number of tones reproduced by the D/A converter of the device under test. Therefore, if a different type of D/A converter is to be tested, there is a need to have an extra non-defective D/A converter of the same type as the D/A converter as a reference D/A converter. The difficulties of the testing device depicted by Japanese Patent Application Laid-Open Hei 9 No.312569 are that there is a need to have a non-defective high-quality reference D/A converter for each type of D/A converter of the device to be tested or for each type of semiconductor integrated circuit incorporating a D/A converter to be tested.
SUMMARY OF THE INVENTION
The present invention has been made in view of the above prior art difficulties, and it is therefore an object of the present invention to provide a testing device and testing method for semiconductor integrated circuits which can markedly reduce the test time and enables a conventional inexpensive testing device to perform highly accurate testing without the necessity of providing a separate reference voltage generator for each type of semiconductor integrated circuit to be tested.
In order to achieve the above object, the present invention is configured as follows:
In accordance with the first aspect of the present invention, a testing device, for a semiconductor integrated circuit which incorporates a multiple number of D/A converters and outputs voltages from the D/A converters via associated output terminals, includes:
a reference voltage generator which generates a multiple number of reference voltages to be compared to each output voltage output from each of the output terminals and can selectively output multiple sets of reference voltages required for testing multiple kinds of semiconductor integrated circuits;
a multiple number of differential amplifiers, each having two input terminals, one for receiving the output voltage output from the associated output terminal and the other for receiving the reference voltage from the reference voltage generator; and
a comparator that receives the amplified output voltages from the multiple number of differential amplifiers and judges whether the amplified output voltage from each of the differential amplifiers falls within a given voltage range.
In accordance with the second aspect of the present invention, the testing device for semiconductor integrated circuits having the above first feature is characterized in that the referenc
Baran Mary Catherine
Hoff Marc S.
Sharp Kabushiki Kaisha
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