Testing components of I/O paths of an integrated circuit

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

Reexamination Certificate

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C324S763010, C324S765010, C714S727000

Reexamination Certificate

active

11308931

ABSTRACT:
Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.

REFERENCES:
patent: 5084874 (1992-01-01), Whetsel, Jr.
patent: 5490151 (1996-02-01), Feger et al.
IEEE Standard Test Access Port and Boundary-Scan Architecture, Test Technology Standards Committee of the IEEE Computer Society, pp. 1-200 (Tables of Contents), Approved Jun. 14, 2001, IEEE-SA Standards Board, The Institute of Electrical and Electronics Engineers, Inc. 3 Park Avenue, New York, NY 10016-5997, USA.

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