Data processing: measuring – calibrating – or testing – Testing system – Of circuit
Reexamination Certificate
2006-06-26
2009-10-13
Barbee, Manuel L (Department: 2857)
Data processing: measuring, calibrating, or testing
Testing system
Of circuit
C702S120000, C324S765010
Reexamination Certificate
active
07603248
ABSTRACT:
A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
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European Search Report for EP 06 25 3423, dated Feb. 15, 2008, 9 pgs.
Mouri Haruyuki
Nakajima Masao
Sugiyama Hidetoshi
Suzuki Hideaki
Arent & Fox LLP
Barbee Manuel L
Fujitsu Microelectronics Limited
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