Testing asynchronous circuits

Details Testing asynchronous circuits Testing asynchronous circuits

1999-01-05

2001-06-12

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C340S514000

Reexamination Certificate

active

06246971

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing integrated circuits (ICs) and, in particular, to automated test equipment (ATE) having improved testing of asynchronous circuits and systems in ICs.
2. Description of the Related Art
Thousands of ICs are often manufactured on a production line. There is a need to detect and reject defective chips, i.e. those that do not produce proper outputs for given inputs. One way to do this is to employ a personal computer (PC)-based testing program, which can be used to test a given chip, typically by applying test inputs to the chip and comparing actual outputs in response thereto to expected outputs. However, the PC-based testing process can be too slow for a mass production run or otherwise undesirable.
Manufactured ICs or chips are, therefore, typically tested by synchronous automated test equipment (an ATE or tester) to ensure the proper functioning of each chip. Typically, an ATE can automatically receive and test a chip in only a few seconds. This is done by the ATE receiving the next chip to be tested, and downloading into the chip a test program containing various test input vectors (applied stimulus) and expected outputs. After executing various instructions operating on the input vectors in accordance with the testing program, one or more outputs are produced, which are compared, typically by a digital signal processor (DSP) of the chip, to the expected output(s). If the results are as expected, the chip outputs a signal indicating “pass”. Otherwise, the chip outputs a “fail” output signal. This signal may be detected by the tester and the chip rejected if a fail signal is detected.
Often such testing is done in accordance with IEEE Std 1149.1-1990 (JTAG) (see http://www.jtag.com or http://www.ieee.org), the so-called JTAG (“Joint Test Action Group”) standard. Thus, each chip contains a special JTAG output pin or port, and the ATE is also JTAG-compatible. The ATE downloads a JTAG testing program into the chip to be tested. The chip then runs the JTAG testing program, which defines the testing procedure that the chip is to follow and the type of output that the chip is to generate in response to the test results. If the chip determines that the chip has passed the test, the chip outputs a special serial bit pattern or vector indicating “pass” on the JTAG output pin, and otherwise outputs a “fail” test output pattern. This pattern is sometimes referred to as a matching pattern or signature, which indicates “pass”. For example, a matching pattern of
0
xACED may be employed. The ATE, coupled to the chip's JTAG output pin, is synchronous and is designed to pass a chip under test only if an expected “pass” test output pattern is detected at a precisely predetermined time. Otherwise, the ATE rejects the chip as being defective.
Referring now to
FIG. 1
, there is shown a timing chart
100
showing illustrative test output comparisons for a prior art ATE. Timing chart
100
comprises row
111
, which shows the expected test output pattern, which is expected to be output by the tested chip starting at precisely time T
2
, if the chip passes the test. The exemplary test output pattern is LHLLHH, where “L” represents a low signal, and “H” represents a high signal. Thus, the JTAG test program causes the chip to run a testing program and to output the “pass” output pattern LHLLHH if the chip determines it has passed the test. The ATE expects this exact pattern, at precisely time T
2
, in cases where the chip is operating properly.
Row
112
shows an example of an early actual test output pattern produced by the chip, which contains the appropriate “pass” test output pattern but which is output by the chip starting two clock cycles too early, at time T
0
. Row
113
shows an example of a late actual test output pattern produced by the chip, which contains the appropriate “pass” test output pattern but which is output by the chip starting two clock cycles too late, at time T
4
. Row
114
shows an example of an on-time actual test output pattern produced by the chip, which contains the appropriate “pass” test output pattern by the chip at exactly the expected time T
2
.
As will be appreciated, the tester or ATE is configured to begin testing for identical bits of the expected test output pattern at time T
2
. Before time T
2
, no testing is done, and testing stops after time T
7
. I.e., testing occurs only during the comparison time period from T
2
to T
7
. If any actual output bit does not match the expected output bit in any of the time slots (clock cycles) of the comparison time period, the tester assumes that the “pass” test output pattern was not produced by the chip, and thus rejects the chip. For example, if a “fail” test output pattern is produced by the chip, or if the chip for any reason fails to output pass test output pattern, it will not match up with the expected output
111
, even if timing is proper.
However, if early output
112
is produced, then at time T
3
a mismatch and thus failure will be detected, even though the chip did put out the appropriate test output pattern (albeit slightly too early) to indicate that it did pass the test. Alternatively, in differently-configured ATEs, a mismatch may be detected earlier, e.g. at times T
0
or T
1
, if the actual “L” or “H” signals output in those time slots are recognized by the ATE as being different from the expected “no output” at those times slots (row
111
).
Similarly, if late output
113
is produced, then at time T
2
a mismatch and thus failure will be detected, even though the chip did put out the appropriate test output pattern (albeit slightly too late) to indicate that it did pass the test.
In some cases, when the appropriate pass test output pattern is output by the chip but it does not start at exactly the expected clock cycle, the detection of a failure can be considered to be a false failure, because although the chip produced a test output pattern slightly too early or too late, the earliness or lateness is not so extreme that the chip, in actual implementation in a larger system, would cause errors or failure. For example, a chip that produces the correct test output pattern or vector on time (row
114
), two cycles too early (row
112
), or two cycles too late (row
113
) may still function acceptably when integrated into a system. Therefore, the foregoing testing devices and procedures sometimes cause functional chips to be falsely rejected, leading to inefficient use of resources.
SUMMARY
In the present invention, a method and system are provided for testing a circuit. A test program is downloaded into the circuit, which causes the circuit to provide a serial test output pattern comprising a series of identical signals to indicate whether the circuit passes the test. Signals of the test output pattern are compared against corresponding signals of an expected test output pattern only for non-masked signals of the expected test output pattern, wherein the expected test output pattern is masked for a maximum tolerable time period around an expected test output pattern start time.


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patent: 4873705 (1989-10-01), Johnson
patent: 5325309 (1994-06-01), Halaviati et al.
patent: 5355369 (1994-10-01), Greenbergerl
patent: 5841786 (1998-11-01), Keyes
patent: 5852617 (1998-12-01), Mote, Jr.

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