Testing associative memory

Details Testing associative memory Testing associative memory

1996-10-03

1998-09-01

Nguyen, Hoa T.

Excavating

371 212, 365 49, 365201, G11C 2900

Patent

active

058020705

ABSTRACT:
A method of testing a first memory such as a RAM having data storage at a plurality of individually addressable storage locations is provided. A portion of the address for the addressable locations of the first memory is supplied as an output from a second memory such as a CAM. The second memory includes a decoder to provide a decoded address as input signals to the second memory. During the testing, first memory specific addresses are provided to the decoder as input. These first memory specific addresses are decoded by the decoder and are gated as input signals to address the first memory. In this way, the decoder which in normal operation provides decoded input signals to the CAM is used to provide input signals to the RAM, thus obviating the need for any scan chain latches surrounding the RAM. This enables conventional testing apparatus to provide the necessary test protocol for the RAM through the decoder normally used by the CAM.

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