Testing apparatus for semiconductor device

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365201, G11C 2900, G11C 700

Patent

active

059178337

ABSTRACT:
A testing apparatus for semiconductor device capable of preventing reduction in the number of devices to be simultaneously measured is provided. Address of a measurement section of a semiconductor device to be measured, input data inputted to the measurement section and expected data to be outputted from the semiconductor device when the input data is inputted are generated by an ALPG. Output data actually outputted from the semiconductor device when the input data is inputted and expected data are compared with each other at a comparison unit. Comparison result is outputted as fail information. By a test pass control unit, there is generated test pass information for selecting fail information on the basis of divisional test information inputted in the case where the cycle time of test is faster than the cycle time of the fail information storage memory. Memory cell within the fail information storage memory is selected on the basis of address of the measurement section. Thus, fail information is written into the selected memory cell on the basis of test pass information by a fail information write control unit.

REFERENCES:
patent: 5410687 (1995-04-01), Fujisaki et al.
patent: 5481671 (1996-01-01), Fujisaki
patent: 5539699 (1996-07-01), Sato
patent: 5835428 (1998-11-01), Kobayashi
patent: 5841785 (1998-11-01), Suzuki

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