Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
2000-09-15
2003-07-15
Cuneo, Kamand (Department: 2829)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S1540PB
Reexamination Certificate
active
06593765
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a testing apparatus and testing method for semiconductor integrated circuits, more specifically a testing apparatus and testing method for semiconductor integrated circuits which have high observability and can readily detect presence and absence of delay faults and stuck-at faults.
Today, semiconductor integrated circuit devices using CMOS logic circuits are widely used. Such semiconductor integrated circuit devices are required to have prescribed performances, and are tested after fabricated as to whether or not they have satisfied the prescribed performances.
In a semiconductor integrated circuit, a path through which signals are propagated is called a path and a delay time from an input signal line, which is a start of the path to an output signal line, which is a terminal of the path is called a path delay time.
Recently, as operational speeds of semiconductor integrated circuits are increased, it is increasingly necessary to measure the path delay time of the semiconductor integrated circuits.
In a conventional path delay fault testing method, in order to detect a delay fault, based on an increase of a path delay time of a path under test, the logic gates of the path under test are activated to propagate a signal transition generated in an input signal line of the path under test to an output signal line of the path under test. Here, “activation” is to switch on all the logic gates of a path under test.
When a delay time of a path under test is longer than a prescribed time, it is judged that the path under test has a path delay fault, and when the delay time of the path under test is shorter than the prescribed time, it is judged that the path under test has no path delay fault.
However, in such a conventional path delay fault testing method, a signal transition generated in an input signal line of a path under test must be propagated to an output signal line of the path under test, and a path under test which can_@not propagate a signal transition to the output signal line cannot be tested. That is, the conventional path delay fault testing method has low observability.
In the conventional path delay fault testing method, to activate a path under test, non-control input values must be inputted to all side inputs which are not on the path under test. It is difficult to satisfy such requirement. Here, a side input is an input line which is not on a path under test. A non-control input value is a logic value which does not uniquely determine an output of each logic gate. For example, non-control input values of an AND gate and a NAND gate are logic value “1”, and non-control input values of an OR gate and a NOR gate are logic value “0”.
In the conventional path delay fault testing method, the above-described restriction is applied to input values to be inputted to side inputs. Accordingly, it is difficult to generate two test patterns which activate a path under test, i.e., a series of test patterns (a test vector pair).
In the conventional path delay fault testing method, it is necessary that hazards (beard-like pulses) are not generated in side inputs so that hazards (beard-like pulses) are not outputted to an output signal line. It is difficult to set side inputs so as to satisfy such condition.
On the other hand, quiescent power supply current testing method (I
DDQ
testing method) is proposed as a testing method which has high observability and can easily generate test patterns. The I
DDQ
testing method does not measure a power supply current in a transient state of a semiconductor integrated circuit, but measures a power supply current in a stable state of the semiconductor integrated circuit. Accordingly, the I
DDQ
testing method cannot measure a path delay time. In other words, the I
DDQ
testing method mainly tests absence and presence of a bridge defect of a semiconductor integrated circuit, and cannot detect an open defect and a parametric defect which are primary factors of a delay fault, i.e., abnormalities of process parameters in the fabrication process.
As a method substituting the I
DDQ
testing method, a testing method (I
DDT
testing method) which measures a transient current value of a power supply current, i.e., an instantaneous value of a transient power supply current has been proposed. The I
DDT
testing method is described in, e.g., M. Sachdev, P. Janssen and V. Zieren, “Defect Detection with Transient Current Testing and its Potential for Deep Sub-micron ICs”, Proceedings of IEEE International Test Conference, pp. 204-213, 1998. Sachdev et al. evaluate the I
DDT
testing method as a method substituting the I
DDQ
testing method, and describe that the I
DDT
testing method is applicable to fabrication tests for deep sub-micron VLSIs. They describe based on results of the experiment that the I
DDT
testing method can detect faults of devices having high levels of background current. They do not refer to a testing method for path delay
Recently, as semiconductor integrated circuits are more integrated, paths under test are on increase. Furthermore, circuit modules of semiconductor integrated circuits are buried at deep layer-levels, which makes it additionally difficult to measure a delay time of the path under test. In order to solve such problems, it has been proposed to design a semiconductor integrated circuit such that a part or all of flip-flops of the semiconductor integrated circuit can be scanned, and contents of the flip-flops can be sequentially read out by external control. In this case, a number of clocks are required to read out the contents of the flip-flops. A test time is accordingly long.
Recently, as semiconductor integrated circuits are more integrated, paths under test for path delay time are on increase. It takes long time to measure the path delay time. Accordingly, increase of the test cost is a recent problem.
Accordingly, a testing method which, for saving test costs, can measure efficiently path delay time of semiconductor integrated circuits, has high observability of path delay time and can easily generate test patterns has been expected.
Furthermore, micro-open defects and resistive open defects are problems. A micro-open defect is a very small line breaking defect taking place in a signal line. A very small amount of tunnel current flows through the micro-open defect. A resistive open defect is a defect in which contact resistance between signal lines becomes higher due to a defective contact than a normal value, and a resistance value of the signal lines becomes higher due to breakage of the signal lines. Current flowing through a resistive open defect becomes smaller than a normal value. When a micro-open defect or a resistive open defect is present in a signal line or others, a transition time of a signal is increased, and accordingly a path delay time becomes longer. A micro-open defect and resistive open defect often increase current flowing through a circuit, and accordingly increase power consumption. Thus, the micro-open defect and resistive open defect are detrimental to realizing semiconductor integrated circuit devices of high speed and low electric power consumption. However, the conventional testing methods cannot efficiently detect the micro-open defect and resistive open defect.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a testing apparatus and testing method for semiconductor integrated circuits, which have high observability and can readily detect delay faults, stuck-at faults, etc.
The above-described object is achieved by a testing apparatus for a semiconductor integrated circuit comprising: test pattern inputting means for inputting to the semiconductor integrated circuit a test pattern sequence for activating a path under test of the semiconductor integrated circuit; transient power supply current measuring means for measuring transient power supply current supplied to the semiconductor integrated circuit while the path under test is being activated; and fault detecting means for judging absence an
Hashimoto Yoshihiro
Ishida Masahiro
Yamaguchi Takahiro
Advantest Corp.
Cuneo Kamand
Muramatsu & Associates
LandOfFree
Testing apparatus and testing method for semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Testing apparatus and testing method for semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testing apparatus and testing method for semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3089663