Testing analog-to-digital and digital-to-analog converters

Details Testing analog-to-digital and digital-to-analog converters Testing analog-to-digital and digital-to-analog converters

2002-06-10

2004-03-09

Williams, Howard L. (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C379S377000, C375S221000

Reexamination Certificate

active

06703952

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to the testing of electronic converters and in particular the testing of analog-to-digital and digital-to-analog converters formed in integrated circuits.
BACKGROUND
Analog-to-digital (A/D) converters convert analog signals to digital signals. Moreover, digital-to-analog (A/D) converters convert digital signals to analog signals. A known method of testing an A/D converter is by applying a select analog test signal to the input of the A/D converter and monitoring the output of the converter for a code word formed from the test signal. If the code word matches an expected code word, the converter is verified as properly working. Similarly, a D/A converter can be tested by applying a select digital signal to an input of the D/A converter and monitoring the output of the converter for an analog signal. If the analog signal matches an expected analog signal, the converter is verified as properly working.
Conventional methods of testing A/D and D/A converters have limitations when the converters are formed as part of an integrated circuit. In particular, one limitation of a converter formed in an integrated circuit is accessing the converters inputs and outputs. That is, in some integrated circuits, there is no way to directly supply a signal to an input or monitor an output of the A/D or D/A converters. An example of an integrated circuit containing A/D and D/A converters that lack direct access to either the inputs or outputs of the A/D and D/A converters is a management card of a shelf unit in a telecommunication network. The lack of direct access to either the inputs or outputs of the A/D and D/A converters makes testing of the A/D and D/A converters difficult. Accordingly, it is desired in the art to have an effective method of testing A/D and D/A converters formed in integrated circuits.
For the reasons stated above and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an effective method of testing A/D and D/A converters formed in integrated circuits.
SUMMARY
The above-mentioned problems with testing A/D and D/A converters and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a method of testing an analog-to-digital (A/D) converter formed in an integrated circuit is disclosed. The method comprises applying an analog test signal of a first frequency to an input of the A/D converter. Sampling digital byte samples from an output of the A/D converter at a second sampling frequency and comparing select digital byte samples with each other. When the select digital byte samples match, storing a verify bit in a memory to verify the A/D converter is working.
In another embodiment, another method of testing an analog-to-digital (A/D) converter formed in an integrated circuit is disclosed. The method comprises applying an analog test signal having a one kilohertz frequency to an input of the A/D converter. Sampling digital byte samples from an output of the A/D converter at an eight kilohertz frequency, wherein each digital byte sample is eight bytes. Comparing first and ninth digital byte samples and when the first and ninth digital samples match, verifying the A/D converter is working properly.
In another embodiment, a method of testing a digital-to-analog (D/A) converter formed in an integrated circuit is disclosed. The method comprises creating repeating digital byte samples with a logic circuit in a gate array formed in the integrated circuit. Converting the repeating digital byte samples into an analog test signal with the D/A converter. Comparing the frequency of the analog test signal with the frequency of an expected analog signal and when the analog test signal frequency matches the expected analog signal frequency, conveying that the D/A converter is working.
In another embodiment, another method of testing a digital-to-analog (D/A) converter is disclosed. The method comprises applying eight byte repeating digital samples to an input of the D/A converter at a frequency of eight kilohertz. Measuring the frequency of an analog output signal from an output of the D/A converter and when the frequency of the output signal is one kilohertz, conveying that the D/A converter is properly working.
In another embodiment, a method of testing an analog-to-digital (A/D) and a digital-to-analog (D/A) converter formed in an integrated circuit is disclosed. The method comprises applying an initial analog signal to an input of the A/D converter. Converting the initial analog signal into repeated digital byte samples with the A/D converter. Applying the repeated digital byte samples to an input of the D/A converter. Comparing an output analog signal of the D/A converter with the initial analog signal and when the output analog signal matches the initial analog signal, conveying that the A/D and D/A converters are properly working.
In another embodiment, an integrated circuit having an analog-to-digital (A/D) converter is disclosed. The integrated circuit includes a test access port and a gate array. The test access port is coupled to an input of the A/D converter. The test access port is adapted to receive an analog test signal of a select frequency. The gate array is coupled to an output of the A/D converter. Moreover, the gate array is adapted to compare select digital byte samples from an output of the A/D converter and to store a verify bit when a match is found, wherein the verify bit indicates the A/D converter is working properly.
In another embodiment, an integrated circuit having a digital-to-analog (D/A) converter is disclosed. The integrated circuit includes a test access port and a gate array. The test access port is coupled to an output of the D/A converter. The test access port is further adapted to receive analog signals from the D/A converter. The gate array is formed in the integrated circuit. The gate array is further adapted to supply repeated digital byte samples of a given frequency to the input of the D/A converter, wherein a tester can be coupled to the test port to measure the frequency of received analog signals in determining if the D/A converter is properly working.
In another embodiment, an integrated circuit having analog-to-digital (A/D) and a digital-to analog (D/A) converters is disclosed. The integrated circuit includes a test access port, a gate array, a loop back circuit and a logic circuit. The test access port is adapted to interface analog signals. The A/D converter has an input coupled to the test access port. The D/A converter has an output coupled to the test access port. The gate array is coupled to an output of the A/D converter and an input of the D/A converter. Moreover, the gate array is adapted to pass through received digital byte samples. The loop back circuit is adapted to receive digital byte samples from the gate array and selectively loop the digital byte samples back through the gate array during testing, wherein if the frequency of a looped back signal at the test access port matches the frequency of an initial test signal applied to the test access port, the A/D and D/A converters are verified as working properly.
In another embodiment, a management card of a shelf unit in a telecommunication network is disclosed. The management card includes a test access port, an analog-to-digital (A/D) converter, a digital-to-analog (D/A) converter and a gate array. The test access port is adapted to selectively interface analog signals to and from an external tester. The A/D converter having an input coupled to the test access port. The D/A converter having an output coupled to the test access port. The gate array is coupled to an output of the A/D converter and an input of the D/A converter. In addition, the gate array is adapted to compare select digital byte samples from the output of the A/D converter and to store a verify bit when a match is found during testing of the A/

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