Testing a device under test by sampling its clock and data...

Details Testing a device under test by sampling its clock and data... Testing a device under test by sampling its clock and data...

2007-08-21

2007-08-21

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C365S233100, C702S080000, C714S738000

Reexamination Certificate

active

11353662

ABSTRACT:
There is provided a method that includes (a) sampling a data signal and a clock signal by applying strobes for obtaining a corresponding bit values each for the data signal and for the clock signal, each of the strobes having a different phase offset with respect to a tester clock signal, (b) deriving first comparison results for the bit values of the data signal by comparing the bit values of the data signal each with an expected data bit value of expected data, (c) deriving second comparison results for the bit values of the clock signal by comparing the bit values of the clock signal each with an expected clock bit value, (d) deriving for the strobes combined comparison results by applying logical operations each on pairs of corresponding first and second comparison results, and (e) deriving a test result based on the combined comparison results.

REFERENCES:
patent: 3731210 (1973-05-01), Mollod
patent: 4876655 (1989-10-01), Carlton et al.
patent: 5835506 (1998-11-01), Kuglin
patent: 6894945 (2005-05-01), Sawada
patent: 2005/0080580 (2005-04-01), Shuusuke
patent: 01164118 (1989-06-01), None
patent: 2000314767 (2000-11-01), None

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