Tester for semiconductor memory devices

Details Tester for semiconductor memory devices Tester for semiconductor memory devices

1989-09-21

1992-10-20

Smith, Jerry

Excavating

371 212, 371 211, G06F 1100

Patent

active

051576643

ABSTRACT:
An offline redundancy memory test system replaces fail memory equipment, under the control of a test system CPU, with fail memory equipment under the control of a second CPU. The second CPU is dedicated to the analysis of the contents of the offline redundancy memory test system fail memory, for redundancy identification and defect pattern analysis, at the conclusion of functional testing. Therefore, in a mass production wafer level memory test system, the test system CPU is free to prepare and execute non-functional tests on the next set of devices to be tested, thereby reducing overall memory test time by the amount of fail memory equipment analysis time previously taken by the test system CPU leading to a reduction in the total number of memory test systems required to provide redundancy memory testing.

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patent: 4797886 (1989-01-01), Imada
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patent: 4905183 (1990-02-01), Kawaguchi et al.
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