Testable redundancy decoder of an integrated semiconductor memor

Details Testable redundancy decoder of an integrated semiconductor memor Testable redundancy decoder of an integrated semiconductor memor

1989-02-10

1990-05-01

Hudspeth, David

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072021, 307449, 365200, 365201, H03K 19003

Patent

active

049221345

ABSTRACT:
A redundancy decoder of an integrated semiconductor memory having a plurality of decoder stages containing a switching transistor and a separable connection having respective conditions in which the separable connection is severed and intact, as well as at least one charging transistor, comprising, in each of the decoder stages, an addressing circuit connected to and between the switching transistor and the separable connection of the respective decoder stages, the addressing circuit being electrically simulatable when the respective separable connection is in the intact condition thereof.

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