Patent
1994-04-15
1996-08-27
Nguyen, Hoa T.
G01R 3128
Patent
active
055509746
ABSTRACT:
A testable memory array (34) has a plurality of TAG-DATA field pairs. Each TAG asserts a MATCHLINE signal if an input tag matches a stored tag. During normal operation, the asserted matchline signal causes the entry to outputs its DATA field. During a testing mode, testing circuitry (50 and 52) gates the matchline signal with the output of a one-of-N decoder (48). Consequently, only one of the various matchline signals can be asserted at any given time regardless of whether test data creates multiple tag matches. The various TAG bit cells can then be connected in scan chains without risk of driving two different DATA FIELDS to the same output bit line.
REFERENCES:
patent: 4631660 (1986-12-01), Woffindent et al.
patent: 4680760 (1987-07-01), Giles et al.
patent: 4760971 (1988-04-01), Tomm et al.
patent: 4982360 (1991-01-01), Johnson et al.
patent: 5107501 (1992-04-01), Zorian
patent: 5263140 (1993-11-01), Riordan
patent: 5276833 (1994-01-01), Auvinen et al.
"Testability Features of the SuperSPARC Microprocessor," Patel et al; 1993 IEEE, International Test Conference.
"VLSI Chip Set for a Multiprocessor Workstation--Part I: An RISC Microprocessor with Coprocessor Interface and Support for Symbolic Processing," Lee, et al; IEEE Journal of Solid-State Circuits; Dec. 1989.
Pennington Artie
Ueda Makoto
Chastain Lee E.
Motorola Inc.
Nguyen Hoa T.
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