Testable LSI device incorporating latch/shift registers and meth

Details Testable LSI device incorporating latch/shift registers and meth Testable LSI device incorporating latch/shift registers and meth

1988-06-24

1990-03-27

Karlsen, Ernest F.

Textiles: spinning, twisting, and twining

371 15, 371 251, 371 223, G01R 3128

Patent

active

049123955

ABSTRACT:
A testable LSI chip incorporating memory blocks, such as RAM and ROM, and random logic circuitry, and a testing method thereof are disclosed. A front-stage peripheral logic circuit block and rear-stage peripheral logic circuit block connected to the input and output modes of a memory block are provided on their output side and input side, respectively, with the flip-flops in correspondence to the input and output nodes of the memory block. The flip-flops on the output side and flip-flops on the input side are each connected to form a shift register. In testing the front peripheral logic block, the test result is latched in the flip-flops on the output side and then the contents are shifted out for reading. In testing the rear-stage peripheral logic circuit block, a bit pattern for testing is shifted-in and latched in the flip-flops on the input side and then supplied to the rear-stage peripheral logic circuit block under test. The front and rear-stage peripheral logic circuit blocks are tested independently of the memory block.

REFERENCES:
patent: 4441075 (1984-04-01), McMahon
patent: 4710930 (1987-12-01), Hatayama et al.

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