1992-02-10
1995-01-10
Beausoliel, Jr., Robert W.
Excavating
371 24, 371 71, G11C 2900
Patent
active
053814185
ABSTRACT:
The present invention operates by verifying correct latch operation in a digital circuit. After a value has been stored in a latch, electronic circuitry can verify that the value has been stored correctly. The electronic circuitry that performs this verification can be tested to insure that it is operating properly. Several latches can be wired into a scan chain and tested with relative ease. Operation of the present invention is illustrated by an enhanced master-slave latch system. In this system, two comparators are used. A first comparator is used to determine if the internal state of the master latch is identical to the signal which had been applied to this latch's data input terminal. A second comparator is used to determine if the state transfer between the master and slave latches occurs properly. Each comparator consists of an EXCLUSIVE-OR function. By placing known logic levels on each input terminal of the comparison circuitry, the output terminal of the comparison circuitry can be examined for an expected logic level to verify that it is operating properly. By placing several latches into a scan chain, a single latch can be loaded with data which will cause an expected signal to appear on the output terminal of this latch's comparison circuitry. This allows for simplified testing of a multiple latch system.
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A CMOS LSSD Test Generation System D. Leet et al. IBM J. Res. Develop. Sep. 1984 pp. 625-635.
Beausoliel, Jr. Robert W.
Chung Phung M.
International Business Machines - Corporation
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