Testable high count counter

Electrical pulse counters – pulse dividers – or shift registers: c – Systems – Using shift register

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377 20, 377 75, G11C 1900

Patent

active

056944446

ABSTRACT:
An integrated circuit counter is capable of implementing a relatively high count while being testable using a relatively low number of clock cycles. A linear-feedback shift register (LFSR) having n bit positions is used as the counter. The feedback path of the shift register includes an exclusive OR (XOR) gate that couples selected bits back to the input of the register, in order to implement a 2.sup.n -1 counter. Combinatorial logic circuitry is included to test the counter in significantly less than 2.sup.n -1 clock cycles. This allows for implementing a testable "watchdog timer" that may be used to detect software runaway conditions in microprocessor systems, among other uses.

REFERENCES:
patent: 5542051 (1996-07-01), Farrell et al.

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