Excavating
Patent
1989-11-06
1992-07-21
Ruggiero, Joseph
Excavating
371 212, G11C 2900
Patent
active
051329735
ABSTRACT:
A system for testing a RAM array bus transaction buffer without halting system operation or using a special protocol, including a RAM control selection circuit for providing to the RAM either a set of normal control, data and address signals or diagnostic control, data and address signals; a Diagnostics Mode Bit Register (DMBR); a Diagnostics Address Register (DAR); and means for recognizing instructions to write to those registers or to a fictitious Diagnostics Data Register (DDR). First a normal write operation is executed to the DMBR, to control a RAM control selection circuit. The RAM control selection circuit chooses as RAM control signal sources a set of diagnostic sources rather than normal system sources. Second, a selected RAM address is written to the DAR. Third, a write operation is performed to the DDR, causing the selected data to be written to the RAM at the address specified by the DAR. Data is similarly read from the RAM through the DDR.
REFERENCES:
patent: 4204251 (1980-05-01), Brudevold
patent: 4903268 (1990-02-01), Hidaka et al.
patent: 4961191 (1990-10-01), Nakagawa et al.
patent: 4969148 (1990-11-01), Nadeau-Dostie et al.
patent: 5012180 (1991-04-01), Dalrymple et al.
Serial Interfacing for Embedded-Memory Testing, Silburt et al., 1990.
Griffin Roland I.
Haggard Alan H.
Hewlett--Packard Company
Lebowitz Henry C.
Ruggiero Joseph
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