Testable digital delay line

Details Testable digital delay line Testable digital delay line

2007-02-13

2007-02-13

Hoff, Marc S. (Department: 2857)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

C702S176000, C702S177000, C702S190000

Reexamination Certificate

active

11117924

ABSTRACT:
A testable digital delay line that uses XOR gates as delay elements is provided. The use of XOR gates enables independent control of each input to the multiplexer. With test inputs that enable each delay element, the multiplexer inputs can be assigned any value during test, thus giving the delay line very robust pattern fault coverage. The XOR gate may consist of three current limiting inverters. A reference voltage generator generates constant voltages between a source voltage, bias voltages, and ground. These constant voltages decide the amount of current through the current limiting inverters. Selecting a different set of reference voltages programs a different current flowing in the current limiting inverters. This programmable current causes a programmable unit delay to be introduced by each XOR gate delay element.

REFERENCES:
patent: 5118975 (1992-06-01), Hillis et al.
patent: 5719515 (1998-02-01), Danger
patent: 6294925 (2001-09-01), Chan et al.
patent: 6388486 (2002-05-01), Schultz
Wang et al., New Efficient Designs for XOR and XNOR Functions on the Transistor Level ,Jul. 1994, IEEE Journal of Solid-State Circuits, vol. 29, 780-786.
Alioto et al., Design of MUX, XOR and D-Latch SCL Gates, 2003, IEEE, 261-264.

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