Testable carriers for integrated circuits

Details Testable carriers for integrated circuits Testable carriers for integrated circuits

1988-09-02

1989-11-07

Fleming, Michael R.

Excavating

371 251, G06F 1100

Patent

active

048797170

ABSTRACT:
A method of testing an interconnection function between two integrated circuits which are mounted on a carrier and which are interconnected by data connections, for example a printed wiring board, is disclosed. The integrated circuits are also connected to a serial bus via which test patterns and result patterns can be communicated between a test device which can be connected thereto and the respective integrated circuits. The bus of a preferred embodiment is formed by a so-called I.sup.2 C bus. In a further elaboration, this set-up can also be used for testing the internal logic circuitry of the integrated circuits. For the testing of the interconnection function, input/output cells with a parallel connection for performing the normal execution function in a transparent mode are provided. They also include series connections for communication test/result patterns by way of a shift register.

REFERENCES:
patent: 4701922 (1987-10-01), Kuboki
patent: 4710930 (1987-12-01), Hatayama
patent: 4710931 (1987-12-01), Bellay
patent: 4710933 (1987-12-01), Powell
patent: 4728883 (1988-03-01), Green

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