Testability architecture and techniques for programmable interco

Details Testability architecture and techniques for programmable interco Testability architecture and techniques for programmable interco

1992-05-26

1993-06-29

Karlsen, Ernest F.

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324158T, 371 28, 307465, 307468, G01R 3100, G01R 3126

Patent

active

052237923

ABSTRACT:
Apparatus for testing for defects in the form of ohmic leakage in an antifuse element disposed between first and second conductors in an integrated circuit prior to formation of electronic circuits by a user, includes circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path to the first conductor during a first time period. Circuitry, responsive to signals provided to the integrated circuit from an external source, is provided to temporarily connect together a second group of the conductors to form a circuit path to the second conductor during the first time period. Circuitry is provided to place an electrical charge onto the first conductor during a second time period within the first time period such that a selected dynamic first voltage potential is placed on the first conductor. Circuitry is provided to drive the second conductor to a second voltage potential different from the selected dynamic first voltage potential during a third time period subsequent to the second time period and within the first time period, wherein the difference between the first voltage potential and the second voltage potential is less than the voltage necessary to cause degradation of the antifuse element. Circuitry is provided to sense the voltage on the first conductor at a predetermined time after the start of the third time period and within the first time period. Circuitry is provided to store a signal related to the voltage on the first conductor at the predetermined time after the start of the third time period. Circuitry is provided to communicate the signal to an input/output pad of the integrated circuit.

REFERENCES:
patent: 3636518 (1972-01-01), van Bosse
patent: 3795859 (1974-03-01), Benante et al.
patent: 3995215 (1976-11-01), Chu et al.
patent: 4004222 (1977-01-01), Gebhard
patent: 4253059 (1981-02-01), Bell et al.
patent: 4259366 (1981-03-01), Balasubramanian
patent: 4380811 (1983-04-01), Gotze et al.
patent: 4409676 (1983-10-01), Varshney
patent: 4418403 (1983-11-01), O'Toole et al.
patent: 4553225 (1985-11-01), Ohe
patent: 4577190 (1986-03-01), Law
patent: 4597062 (1986-06-01), Asano et al.
patent: 4612630 (1986-09-01), Rosier
patent: 4617478 (1986-10-01), Hartmann et al.
patent: 4651304 (1987-03-01), Takata
patent: 4658380 (1987-04-01), Eby
patent: 4700088 (1987-10-01), Tubbs
patent: 4719418 (1988-01-01), Flaker
patent: 4725985 (1988-02-01), Ogura et al.
patent: 4751679 (1988-06-01), Dehganpour
patent: 4864165 (1989-09-01), Hoberman et al.
patent: 5065090 (1991-11-01), Ghuwala
patent: 5068604 (1991-11-01), Van de Laglmaat

Affiliated with

Also associated with

Rating

Testability architecture and techniques for programmable interco does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Testability architecture and techniques for programmable interco, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Testability architecture and techniques for programmable interco will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1758261