Test verification of processor architecture having a partial ins

Details Test verification of processor architecture having a partial ins Test verification of processor architecture having a partial ins

1982-12-15

1985-05-28

Smith, Jerry

Boots, shoes, and leggings

371 16, 371 25, G06F 1100

Patent

active

045204403

ABSTRACT:
A method for verifying the architectural integrity of a newly written or modified instruction set in a limited operating environment is described. More particularly, this methodology is adapted to perform such verification even though the processor under test has only a one or a few instructions in its partially complete instruction set. Such verification is accomplished using a minimum test driver, under control of a test processor, which loads the data necessary to execute the instruction being tested. The test system also provides actual or simulated I/O capabilities. After execution of that instruction, the test driver directs capture of the execution results for appropriate use. As an aid in performing the verification test, the test driver is provided with an invalid command that forces return of control to the test processor. In operation, the processor to be microcoded is tested instruction by instruction, via shared memory, with microcode corrections being made on the same basis to avoid error propagation into the remainder of the instruction set as it is developed.

REFERENCES:
patent: 3544777 (1970-12-01), Winkler
patent: 4231087 (1980-10-01), Hunsberger et al.
patent: 4312066 (1982-01-01), Banz et al.
patent: 4429368 (1984-01-01), Kurii

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