Electrical computers and digital processing systems: processing – Processing architecture
Reexamination Certificate
1998-07-15
2001-04-24
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing architecture
C703S021000
Reexamination Certificate
active
06223272
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to regression testing and, more particularly, to a vector verifications system for increasing the speed at which regression tests may be executed.
2. Description of the Prior Art
Modern electronic hardware design of circuit boards and microprocessors, including microcontrollers and application specific integrated circuits (ASIC), oftentimes necessitates the use of software simulation and/or hardware emulation to verify that the hardware design being tested is functional. In particular, semiconductor companies generally must endure a long and complicated process of prototyping, testing and debugging to ensure that a designed part will work properly.
Verification testing is generally performed through regression testing wherein a large number of test vectors are run. Test vectors specify the expected functional operation of a chip or other device by defining the outputs as a function of the inputs for a certain number of clock cycles. Regression testing involves running the test vectors to exercise some functionality of the device and to determine that some functionality in the device model, which has worked at some point, continues to work as the design evolves.
As ASIC densities exceed one million gates and chip densities approach ten million transistors, design verification becomes a critical factor. Software simulation is the method that has historically been used to verify the Boolean logic of a design. Typically, software based simulators are event-driven. That is, every active signal is determined for every device it propagates through during a clock cycle. As such, software simulation is a relatively slow and inaccurate process and, used alone, is unable to capture all the intricacies of a complex chip. Cycle based simulators are also available, and provide performance gains in verifying Boolean logic. However, cycle-based simulators sacrifice functionality for performance.
Hardware emulation, unlike software emulation, allows engineers to model chip designs in hardware. This is accomplished by mapping the design onto reprogrammable circuitry. The resulting product is a functional equivalent of the actual chip that is able to function at close to real time, able to assure correct timing relationships and run real software. Thus, it can be seen that hardware emulation is faster and more accurate than software simulation. However, use of both software simulation and hardware emulation provides for generally more accurate verification than any single method alone.
Typically, in situations where software simulation and hardware emulation are both used, the software simulator is used to generate outputs based on a number of given inputs. These input vectors are then downloaded to a hardware emulator to serve as inputs, and used to generate output vectors. The output vectors from the hardware emulator are then compared with those of the software simulator. The comparison is done by either downloading the output results from the simulator to the emulator and then having the emulator compare the outputs or by uploading the output results from the hardware emulator to the software simulator and then comparing the results on the simulator. If the outputs do not match, then it can be assumed that either the hardware design or the software simulator is flawed.
Unfortunately, although increased computing power and more powerful hardware have increased the speed of execution of testing on software simulators and hardware emulators, vector comparison remains one of the greatest time consuming operations. In particular, many hardware emulation techniques spend 90% of the time required for regression testing on vector download and only 10% of the time simulating the hardware. Furthermore, oftentimes vector verification is performed manually, further increasing the amount of time vector verification takes. As each generation of the devices becomes increasingly dense, the number of transistors or gates increase, thereby increasing the number of regressions that must be run. Accordingly, this leads to an increase in the number of test vectors that must be downloaded into the hardware emulator or uploaded to the software simulator. Accordingly, comparison time for verifying the output vectors also increases. Currently, for example, running a regression on a microcontroller having fewer than one million transistors may require along the lines of 1000 tests with each test requiring 1000 one-cycle vectors and having a bit value of 1000. This results in a total of one billion bits that must be downloaded or uploaded and then verified. For very dense microprocessors, the above numbers increase dramatically.
What is needed, therefore, is a system for enabling efficient and fast comparison of output vectors in order to decrease the amount of time required to run regression tests.
SUMMARY OF THE INVENTION
Briefly, the present invention relates to a verification system for verifying whether output vectors from a software simulator match the output vectors from a hardware emulator by comparing a pair of checksum values. A first checksum value is calculated from the output vectors obtained from the software simulator and a second checksum is calculated from the output vectors obtained from the hardware emulator. Accordingly, only a checksum value is required to be downloaded or uploaded, thereby eliminating the need to upload or download large numbers of output vectors. In particular, the system includes a software simulator for generating a set of input and output test vectors, a checksum calculator for calculating the checksum of the vector outputs generated by the software simulator, a hardware emulator for receiving and storing the vector inputs and the checksum value generated by the software simulator and for generating output vectors based on the downloaded input vectors, a checksum calculator for calculating the checksum of the vector outputs generated by the hardware emulator and a checksum comparator for comparing the checksums.
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Dictionary of Computers Information Processing & Telecommunications 2nd Ed. by Jerry M. Rosenberg, John Wiley & Sons Pub. p. 205, 1987.
Coehlo Paul R.
Fu Yeh-Chen
Gautho Manuel O.
Coleman Eric
Siemens Aktiengesellschaft
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