Test vector compression/decompression system for parallel proces

Details Test vector compression/decompression system for parallel proces Test vector compression/decompression system for parallel proces

1995-06-28

1997-12-09

Cosimano, Edward R.

Excavating

324 731, 364579, 364580, 39518308, G01R 313183, G06F 11263, G06F 11273

Patent

active

056967721

ABSTRACT:
An integrated circuit (IC) tester includes several processing nodes, each accessing a separate terminal of an IC to be tested. The tester receives as input a description of an integrated circuit test to be conducted. The description indicates actions to be taken at each processing node and a time relative to the start of the test that each action is to be taken. The actions may include transmitting a test signal to the IC or sampling an output signal produced by the IC. Before starting the test, the tester converts the description into a set of algorithms for generating test vectors and stores each algorithm in a separate processing node. The test is organized into a succession of test cycles and during the test, each node executes its stored algorithm, generating a separate test vector at the beginning of each test cycle. The test vector indicates an action to be taken by that node during the following test cycle along with a time during the test cycle that the action is to be taken. Each node includes circuits for executing the action at the time indicated.

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