Test validation method for a semiconductor memory device

Details Test validation method for a semiconductor memory device Test validation method for a semiconductor memory device

1992-08-06

1994-05-03

Atkinson, Charles E.

Excavating

365201, G01R 3128

Patent

active

053094468

ABSTRACT:
A test validation process for a semiconductor device applies signals indicating a test mode to the semiconductor device. The device produces output signals and the output signals are read to determine whether the device is in the indicated test mode. The test mode is conducted by operating the device. The output signals are read upon completion of the test mode to determine if the device is still in the indicated test mode. The test validation method is useful for memory chips and particularly Dynamic Random Access Memory, DRAM, devices that are burn-in stress tested.

REFERENCES:
patent: 4689791 (1987-08-01), Ciuciu et al.
patent: 4706208 (1987-11-01), Helms
patent: 5072137 (1991-12-01), Slemmer
G. Ost, The Practice and Economy of Burn-In, Electronic Engineering, Aug. 1986, pp. 37-40, 43.

Affiliated with

Also associated with

Rating

Test validation method for a semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Test validation method for a semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test validation method for a semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2121216