"Test under mask high" instruction and "Test under mask low" ins

Details "Test under mask high" instruction and "Test under mask low" ins "Test under mask high" instruction and "Test under mask low" ins

1998-09-29

2000-09-19

Donaghue, Larry D.

Electrical computers and digital processing systems: processing

Instruction fetching

712226, G06F 900, G06F 906

Patent

active

061227307

ABSTRACT:
An arithmetic method and apparatus for executing a TMH (Test under Mask High) and a TML (Test under Mask Low) instruction. This apparatus comprises a circuit for detecting that the result of an AND operation performed on a test mask and an operand is "0", which represents the condition for setting a condition code at "0", a circuit for detecting an operand bit corresponding to the leftmost bit of the test mask which is the condition for setting the condition codes at "1" and "2", a circuit for detecting that the result of an OR operation performed on an inverted test mask and the operand is all zeros, which is the condition for setting the condition code at "3", and a circuit for producing a proper condition code based on the outputs of those circuits.

REFERENCES:
patent: 4967351 (1990-10-01), Zmyslowski et al.
Boggs, Jr. , IBM TDB vol. 20 No. 1 pp. 106-107 ; Jun. 1977.
Bechdel et al. , IBM TDB vol. 19 No., 1 pp. 65-66 Jun. 1976.

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