Test terminal negation circuit for protecting data integrity

Details Test terminal negation circuit for protecting data integrity Test terminal negation circuit for protecting data integrity

2006-03-07

2006-03-07

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Floating gate

Data security

C365S185090

Reexamination Certificate

active

07009879

ABSTRACT:
A test terminal negation circuit comprises a switch circuit which receives a test signal from a test terminal and outputs it in an asserted state as it is or in a predetermined negated state to a test object circuit, a test signal control circuit which controls an output signal of the switch circuit to be asserted or negated, a test mode signal generation circuit which generates a test mode signal which asserts the output signal of the switch circuit, and a negating signal generation circuit which can output a negating signal for forcing the output signal of the switch circuit into negated state and comprises an electrically rewritable nonvolatile memory element. When the test signal control circuit receives the negating signal, it does not assert the output signal of the switch circuit even it receives the test mode signal.

REFERENCES:
patent: 5870342 (1999-02-01), Fukuda
patent: 6424142 (2002-07-01), Kato et al.
patent: 6747905 (2004-06-01), Ho
patent: 6839293 (2005-01-01), Kawamoto et al.
patent: 2002/0034112 (2002-03-01), Tetsuo et al.
patent: 2003/0198082 (2003-10-01), Silverbrook et al.
patent: 2002-269523 (2002-09-01), None
patent: WO-01/59571 (2001-08-01), None

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