Test techniques for a delay-locked loop receiver interface

Pulse or digital communications – Synchronizers – Network synchronizing more than two stations

Reexamination Certificate

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C327S158000

Reexamination Certificate

active

07817761

ABSTRACT:
An integrated circuit includes a variable delay circuit configured to generate at least one delayed clock signal based on a first clock signal and a first control signal. The integrated circuit includes a control circuit configured to generate a count value based on a second input signal and a second control signal. The first clock signal is a first version of the at least one delayed clock signal. At least one of the second input signal and the second control signal is a second version of the at least one delayed clock signal and the count value is indicative of a frequency characteristic of the at least one delayed clock signal. The integrated circuit is configured to monotonically vary the first control signal over a range of values and the count value is determined for individual values of the control signal.

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