Test system providing testing sites for logic circuits

Details Test system providing testing sites for logic circuits Test system providing testing sites for logic circuits

1985-03-28

1987-07-21

Smith, Jerry

Excavating

391 25, 324 73R, G06F 1100

Patent

active

046823298

ABSTRACT:
A test system for a logic circuit in which virtual pins are coupled between logical networks and in which the virtual pins are free of any logic elements in common with the networks. A single latch control line, independent of the system clock of the networks, by applying three different control signals, controls switching between a test mode and a system mode and also controls latching and storing of data from a logic network. When the latch control line switches to the system mode it maintains the system mode independently of the cycling of the system clock. Further in the system mode, the virtual pins are transparent. In the test mode a string of virtual pins form a shift register which may be used to shift a test pattern by means of separate A,B clock signals into position for testing the logic networks.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 4225958 (1980-09-01), Funatsu
patent: 4293919 (1981-10-01), Dasgupta
patent: 4308616 (1981-12-01), Timoc
patent: 4534028 (1985-08-01), Trischler
patent: 4566104 (1986-01-01), Bradshaw
L. A. Stolte, "Design for Testability of the IBM System/38", Proc. No. 20th, IEEE Test Conference, 10/1979, pp. 29-36.
E. I. Muehldorf, "Designing LSI Logic for Testability", Proc. No. 7th, Semiconductor Test Conference, 10/1976, pp. 45-49.
S. Dasgupta, "Mult-Function Latch for Shift Register . . . ", IBM Tech. Bulletin, vol. 21, No. 9, 2/1979, pp. 3646-3648.
S. Funatsu, "Designing Digital Circuits with Easily . . . ", IEEE, 2/1978, pp. 98-102.
E. B. Eichelberger, "A Logic Design Structure for LSI Testability", IBM, pp. 462-468.

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