Test system integrated on a substrate and a method for using suc

Electricity: measuring and testing – Measuring – testing – or sensing electricity – per se – With rotor

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324 731, G06F 1100, G01R 3128

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active

053131584

ABSTRACT:
Integrated circuits are arranged in a regular pattern on a semiconductor wafer. The circuits are separated from one another by kerf areas. These kerf areas are used to accommodate test structures from which process parameters can be derived. Because the surface area of these kerf areas is comparatively small, it is necessary to minimize the number of bonding pads or connection terminals for these test structures. The test system is extended with a multiplex circuit whereby a test structure can be selected from the test system and which connects one of the various test structures to always the same connection terminals. Furthermore, using one stimulus which is applied to a connection terminal and which is also the stimulus for the test structure whose response is to be measured, the desired test structure is selected. This is because the multiplex circuit detects on which connection point the stimulus is received and decodes the test structure to be connected to the connection terminals on the basis of the connection pin number.

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patent: 5012185 (1991-04-01), Ohfuji
Nishimura et al.; "Multiplexed Test Structure; A Novel VLSI Technology Development Tool"; IEEE VLSI Workshop on Test Structure; Feb. 17-18, 1986; pp. 336-355.

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