Test system for segmented memory

Details Test system for segmented memory Test system for segmented memory

1980-07-31

1985-01-22

Moffitt, James W.

Static information storage and retrieval

Addressing

Sync/clocking

365201, G11C 700

Patent

active

044956037

ABSTRACT:
A semiconductor memory system is organized into a plurality of segments and is equipped with multiplexed or multifunctional pin for input/output purposes; e.g. the memory address pins, since there is a portion of each memory cycle during which the logic state of the address pins is unimportant. Logic means is provided for coupling the multiplexed pins to the memory segments through the input/output lines upon the occurrence of a test clock signal. The test clock signal is generated during the don't-care portion of the memory cycle.

REFERENCES:
patent: 3311890 (1967-03-01), Waaben
patent: 3336579 (1967-08-01), Heymann
patent: 3845476 (1974-10-01), Boehm
patent: 4061908 (1977-12-01), de Jonge
patent: 4122540 (1978-10-01), Russell et al.

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