Test system for random access memory

Details Test system for random access memory Test system for random access memory

1987-09-18

1989-07-18

Fleming, Michael R.

Excavating

365201, G06F 1100

Patent

active

048499730

ABSTRACT:
A test system for a random access memory includes a clock pulse width varying unit for varying a pulse width of driving pulses for a random access memory. A first latch is connected to an address input circuit of the random access memory for receiving the output clock signal of the clock pulse width varying unit and latching an address input signal at the leading edge of the output clock signal. A second latch is connected to a data output circuit of the random access memory for latching a data output signal. Both the first and second latches are supplied with the same clock signals from the clock pulse width changing unit, and a comparison unit is connected to a data output circuit of the random access memory for comparing the output of the random access memory with a predetermined expectation value. The output of the comparison unit is latched by the trailing edge of the clock pulse in the second latch.

REFERENCES:
patent: 4430735 (1984-02-01), Catiller
patent: 4519077 (1985-05-01), Amin
patent: 4755970 (1988-07-01), Schrenk

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