Test system for integrated circuits with serdes ports

Details Test system for integrated circuits with serdes ports Test system for integrated circuits with serdes ports

2006-06-06

2006-06-06

Barlow, John (Department: 2863)

Data processing: measuring, calibrating, or testing

Testing system

Of circuit

Reexamination Certificate

active

07058535

ABSTRACT:
A system for testing an integrated circuit device under test (DUT) communicating though synchronous digital signals and through a high speed serialization/de-serialization (serdes) bus includes a serdes interface circuit for communicating with the DUT via the serdes bus and an integrated circuit (IC) tester for communicating with the DUT and with the serdes interface circuit via digital signals. State changes in the digital signals are synchronized to a clock signal within the IC tester. The serdes interface circuit receives instructions from the IC tester via at least one of the digital signals and responds to the instructions by transmitting data to the DUT via the serdes bus using appropriate serdes protocol, by receiving and storing data transmitted by the DUT via the serdes bus, and by thereafter forwarding the stored data to the IC tester via at least one of the digital signals.

REFERENCES:
patent: 6694462 (2004-02-01), Reiss et al.
patent: 2003/0105607 (2003-06-01), Jones et al.
patent: 2005/0044463 (2005-02-01), Frisch

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