Semiconductor device manufacturing: process – With measuring or testing – Optical characteristic sensed
Reexamination Certificate
2002-07-02
2003-09-09
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
Optical characteristic sensed
C438S014000, C438S003000
Reexamination Certificate
active
06617178
ABSTRACT:
BACKGROUND
1. Technical Field
The present invention relates generally to testing semiconductor material combinations and more specifically to test ferroelectric
2. Background Art
As the electronic industry develops, several trends drive the development of new technologies. First, people want smaller and smaller products, which require less frequent replacement of batteries, such as cell phones, personal sound systems, digital cameras, etc. Second, in addition to being smaller and more portable, these products are required to have more computational power and more memory storage capability. Third, these devices are expected to maintain information, pictures, etc. even when the batteries die.
Non-volatile memories such as electrically erasable programmable read only memories (EEPROMs), and flash EEPROMs are used in such products because they can maintain data without power. These memories include arrays of memory cells, in which each memory cell includes a memory cell capacitor and a memory cell access transistor.
A new type of non-volatile memory is currently being developed which is based on ferroelectric materials and is called a ferroelectric memory or FeRAM. At this point, there are many different ferroelectric materials and a vast number of different formulations of ferroelectric materials that are being investigated. Since a memory cell must maintain data without power, the memory cell's material must be capable of holding the electrical charge, which represents one bit of data. Thus, one of the key characteristics of the ferroelectric materials, which must be determined and improved, is its charge retention capability or capacitance.
The capacitance of a given capacitor is a function of the dielectric constant of the capacitor dielectric, the effective area of the capacitor electrode, and the thickness of the capacitor dielectric layer. Essentially, decreasing the thickness of the dielectric layer, increasing the effective area of the capacitor electrodes, and increasing the dielectric constant of the capacitor dielectric can increase the capacitance. For smaller products, it is desirable to have a small thickness and a high capacitance.
Decreasing the thickness of a capacitor dielectric layer below 100 Å generally reduces the reliability of the capacitor, because Fowler-Nordheim hot electron injection may create holes through the thin dielectric layers.
Increasing the effective area of the capacitor electrode generally results in a more complicated and expensive capacitor structure. For example, three dimensional capacitor structures such as stack-type structures and trench-type structures have been applied to 4 MB DRAMs, but these structures are difficult to apply to 16 MB or 64 MB DRAMs. A stack-type capacitor may have a relatively steep step due to the height of the stack-type capacitor over the memory cell transistor and trench-type capacitors may have leakage currents between the trenches when scaled down to the size required for a 64 MB DRAM.
Increasing the dielectric constant of the capacitor dielectric requires the use of relatively high dielectric constant materials. Currently, silicon dioxide (SiO
2
) with a dielectric constant around ten is used. Higher dielectric constant materials, such as yttria (Y
2
O
3
), tantalum oxide (Ta
2
O
5
), and titanium oxide (TiO
2
), have been tried. In addition, ferroelectric materials which have even higher dielectric constants, such as PZT (PbZr
x
Ti
(1−x)
O
3
), BST (Ba
x
Sr
(1−x)
TiO
3
), or STO (SrTiO
3
), have been used to provide a new family of memories called ferroelectric random access memories (FRAMs).
Materials such as PZT, SrBi
2
Ta
2
O
9
and (BiLa)
4
Ti
3
O
12
, Bi
3
Ti
4
O
12
are ferroelectric at room temperature and become paraelectric only at temperatures as high as 450C. As such they exhibit a hysteresis in their charge-field response and have a remnant charge even at zero field at room temperature. Further, either a positive or a negative charge can be stored depending on the applied field thus naturally offering two states representing “1” or “0” data bits. Thus, these materials make good non-volatile memories.
BST and STO are ferroelectric materials but only at or just below room temperature. At room temperature they are paraelectric materials, i.e. linear dielectrics, which makes them appropriate for dynamic random access memories. The idea behind trying to integrate BST or STO in memories was to take advantage of their high dielectric constant to thereby enable scaling to lower equivalent oxide thicknesses.
Unfortunately, it was found that trying to take advantage of the high dielectric constant of STO and BST ferroelectrics by scaling to lower equivalent oxide thickness resulted in other problems. Capacitors using ferroelectric materials would be subject to leakage currents, which would discharge the capacitors and effectively decrease the dielectric constant of the ferroelectric materials. For example, BST would have a dielectric constant around 400 to 500 but the dielectric constant would be reduced to around 20 to 50 in a capacitor.
After investigation, it was discovered that the electrodes on both sides of the ferroelectric material were the sources of the problem. The interface between each electrode and the ferroelectric material has an interfacial capacitance, which acts in parallel with the capacitance of the ferroelectric material. Where the interfacial capacitance is low, the capacitance of the combination with the ferroelectric material will be low despite having a high dielectric constant ferroelectric material.
Fortunately, non-volatile memories based on materials such as PZT, SBT, BLT and BiTi—O that are ferroelectric at room temperature do not have to be scaled down to 10 nm thickness range. Typical thickness used is of the order of 100 nm. As such the interfacial properties are not dominant. Furthermore, it has been discovered that the endurance of the capacitors can be improved by the use of a combination of the ferroelectric material and a noble metal electrode of a noble metal such as platinum (Pt) or iridium (Ir) or their oxides and perovskite electrodes such as LaNiO
3
and SrRuO
3
. However, the degree of improvement could only be measured by manufacturing complete devices with different ferroelectric materials and noble metal electrodes, and testing each one of them. With the vast number of different chemical combinations of the ferroelectric layer possible, this process of characterizing the combinations becomes extremely expensive and time consuming.
It has also been discovered that an adhesion layer is required between the bottom electrode (BE) and the substrate since invariably the lower electrode delaminates at the TEOS/BE interface when trying to delineate capacitors by etching but there has been no way of characterizing these combinations also.
It has been found that for lower size substrates, 2 to 4 inches, LaAlO
3
or Al
2
O
3
substrates can be used for test structures, but 8 inch substrates cannot be used due to prohibitive costs or the impossibility of preparing such substrates.
Solutions to this problem has been long sought, but have long eluded those skilled in the art.
DISCLOSURE OF THE INVENTION
The present invention provides a method for ferroelectric layer testing. An adhesion layer is deposited over a semiconductor substrate to be of a phase pure material lacking a first material. A lower electrode is deposited over the adhesion layer and a ferroelectric layer is deposited over the lower electrode. The ferroelectic layer contains the first material. The ferroelectric layer is x-rayed and the x-ray fluorescence from the ferroelectric layer is detected for characterizing the ferroelectric layer. The method provides an inexpensive and quick method for characterizing vast numbers of different combinations of the ferroelectric layer.
REFERENCES:
patent: 5483568 (1996-01-01), Yano et al.
patent: 6096434 (2000-08-01), Yano et al.
patent: 6127218 (2000-10-01), Kang
patent: 6144060 (2000-11-01), Park et al.
patent: 6328433 (2001-12-01), Moriy
Aggarwal Sanjeev
Singh Kaushal K.
Agilent Technologies , Inc
Isaac Stanetta
Niebling John F.
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