Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1997-09-05
2001-04-10
Smith, Matthew (Department: 2825)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C716S030000, C326S121000, C257S344000, C438S327000
Reexamination Certificate
active
06216099
ABSTRACT:
TECHNICAL FIELD
The invention relates to testing integrated circuits and more particularly to evaluating performance and hot carrier reliability of critical path circuitry including transistors of different, very deep sub-micron channel lengths.
BACKGROUND ART
Due to hot carrier effects, which are pronounced in sub-micron geometries, there is a tradeoff between performance and reliability when selecting an appropriate channel length for field-effect transistors, such as MOSFETs or IGFETs. A shorter channel length creates a correspondingly greater electric field between the source and the drain of the transistor, which increases drive current (I
D
) On one hand, an increased drive current due to a shorter channel length is able to more rapidly charge or discharge the load capacitance of the transistor. Consequently, a circuit including the transistor can run at higher frequencies. On the other hand, an increased electric field, particularly near the drain region, causes an increase in “hot carrier” effects, in which accelerated electrons ionize the silicon lattice, generating pairs of electrons and holes. Over time, these hot carriers break bonds and become trapped, changing electrical properties of the transistor. In NMOS transistors, electron mobility is degraded, causing a reduction in the drive current and hence performance of the transistor.
By industry convention, the lifetime of a transistor is the stress time that elapses until there is a 10% reduction in the drive current due to hot carrier effects. Compensating for the reduction in drive current by increasing the source-to-drain potential difference (V
DS
), however, increases local electric fields and rate of hot carrier degradation.
In order to enhance microprocessor speed, we have been investigating the use of sub-minimum (i.e., very deep sub-micron, around 0.25 micron) channel length transistors in stacked NAND gate circuits, commonly part of a microprocessor's critical path. A critical path of a microprocessor is a series of interconnected gates, registers, and other elements through which a propagation delay is determinative of the processing speed of the microprocessor. Therefore, reducing the propagation delay of any element, for example, a NAND gate, in the critical path enables the microprocessor to execute at higher speeds.
Referring to
FIG. 1
, depicted is a three-input stacked NAND gate
100
implemented in CMOS technology, comprising three PMOS transistors
102
,
104
, and
106
coupled in parallel and three NMOS transistors
112
,
114
, and
116
coupled in series. The three-input stacked NAND gate
100
is merely illustrative, because stack NAND gates in a critical path of a microprocessor may comprise up to at least sixteen inputs. In a stacked NAND circuit, the V
DS
for each NMOS transistor is typically much less than the supply voltage, especially for the second and third transistors
114
and
116
. Since the associated hot carrier effects are smaller due to a smaller electric field, the performance of NMOS transistors
112
,
114
, and
116
can be improved by reducing their channel lengths as much as possible while maintaining respective device lifetimes within acceptable norms, commonly specified at five or ten years. Since the V
DS
for each NMOS transistor
112
,
114
, and
116
is different from the others, performance and reliability can be improved by using different channel lengths for the transistors. For example, NMOS transistors
112
,
114
, and
116
may have channel lengths of 0.25 micron, 0.225 micron, and 0.2 micron, respectively. NMOS transistor
112
has the greatest potential difference, V
DS
, across it and hence the longest channel length.
In microprocessor design, it is desirable to accurately predict the performance and reliability of the sub-minimum channel transistors in the stacked NAND gates in the critical path of the microprocessor. However, stacked NAND gates and other critical path circuitry are not easily found or readily available as test structures for evaluating hot carrier effects.
SUMMARY OF THE INVENTION
There exists a need for accurately predicting the performance and hot carrier reliability of circuitry including stacked NAND gates with sub-minimum channel length transistors. There is also a need for a testing methodology that can use readily available test structures.
These and other needs are met by the present invention, which evaluates a circuit by simulation, using a transistor model calibrated by empirical data from a ring oscillator experiment. Ring oscillators are readily available test structures, and calibrating a transistor model in a hot carrier reliability simulation of an integrated circuit enables more accurate prediction of the performance and reliability of the circuit.
Accordingly, one aspect of the invention is a method of analyzing an integrated circuit, such as a critical path for a microprocessor that includes a stack NAND gate having two or more NMOS transistors coupled in series, each with a channel length less than 0.5 micron, preferably less than 0.25 micron. The method comprises the step of fabricating one or more ring oscillators according to the fabrication technology of the integrated circuit. The method further comprises measuring reliability data, e.g. frequency degradation over time, from operating the one or more ring oscillators, calibrating a transistor model based on the reliability data, and simulating the integrated circuit according to the calibrated transistor model. Preferably, the reliability data is measured for a plurality of different stress voltages and channel lengths.
According to another aspect of the invention, a test system for analyzing an integrated circuit to be fabricated according to a given fabrication technology comprises a circuit simulator, such as a computer programmed with simulation software, for simulating the integrated circuit according to an aged transistor model. The system includes one or more ring oscillators fabricated on a wafer, preferably with the integrated circuit, according to the given technology. A measurement system can be coupled to one of the ring oscillators for measuring reliability data, such as frequency degradation over time, from operating the ring oscillator for a prescribed period of time. A calibration system is configured to calibrate the aged transistor model based on the reliability data.
Additional objects, advantages, and novel features of the present invention will be set forth in part in the description which follows, and in part, will become apparent to those skilled in the art upon examination or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
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Fang Peng
Shabde Sunil
Advanced Micro Devices , Inc.
Siek Vuthe
Smith Matthew
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