Test structure for monitoring overetching of silicide during con

Details Test structure for monitoring overetching of silicide during con Test structure for monitoring overetching of silicide during con

1997-04-24

2000-07-11

Powell, William A.

Semiconductor device manufacturing: process

Including control responsive to sensed condition

Electrical characteristic sensed

438721, 438 13, H01L 21302

Patent

active

06087189&

ABSTRACT:
For the contact opening in advanced IC processing, it becomes critical to monitor the degree of overetching of the thin silicide layer and also to obtain the etching rate of the silicide layer. A method is disclosed which will allow the electrical measurements of the sheet resistance of the exposed (by the contact etch) silicide layer, thus allowing electrical measurements to the integrity as well as the thickness of the remaining silicide layer. A main feature of the disclosed test method is a modification of the conventional van der Pauw test structure, or of the cross-bridge structure (which will allow electrical measurement of the line width, in addition to the sheet resistance information). Contrary to the conventional van der Pauw structure or cross-bridge structure where the contact opening pattern is designed to expose only the specific areas needed for allowing electrical connection to the four measurement pads, the contact opening mask is designed to expose some or all of the van der Pauw or cross-bridge structure, thus allowing the electrical measurement of the degree of silicide overetching during contact opening. The disclosed test method and corresponding structure can be applied as an on-wafer process monitor tool following the complete normal process flow, thus serving as a convenient on-wafer monitor.

REFERENCES:
patent: 5362356 (1994-11-01), Schoenborn
patent: 5450205 (1995-09-01), Sawin et al.
patent: 5552718 (1996-09-01), Bruce et al.

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