Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-02-10
2002-03-19
Metjahic, Safet (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010
Reexamination Certificate
active
06359461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to forming a test structure that may be used to determine the distinct properties of each transistor densely packed within the integrated circuit.
2. Description of the Related Art
Fabrication of a MOSFET device is well known. Generally speaking, MOSFETs are manufactured by placing an undoped polycrystalline silicon (“polysilicon”) material over a relatively thin gate oxide. The polysilicon material and the gate oxide are then patterned to form a gate conductor with source/drain regions adjacent to and on opposite sides of the gate conductor. The gate conductor and source/drain regions are then implanted with an impurity dopant species. If the impurity dopant species used for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (“n-channel”) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (“p-channel”) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single substrate. While both types of devices can be formed, the devices are distinguishable based on the dopant species used.
Semiconductor fabrication involves producing a large number of identical integrated circuit devices upon a unitary semiconductor substrate in an array of rectangular elements called “dice”. A few of those devices may be devoted to electrical testing while a majority of the devices are individually packaged to be used as computer hips. Reserving test areas of the substrate for electrical testing is necessary to ensure that functional devices are being manufactured. Further, the properties of the test devices (or test structures) are determined to ensure that optimum device performance is being achieved for the manufactured devices. Several transistor properties, e.g., drive current, I
D
, and subthreshold current, I
Dst
, may be determined using electrical testing of such test structures. Because of the increased desire to build faster and more complex integrated circuit devices, it has become necessary to form relatively small, closely spaced multiple transistors within a single integrated circuit device. Unfortunately, as the packing density of transistors within integrated circuit devices, and hence test structures increases, it becomes more difficult to electrically test a particular transistor within a dense grouping of transistors.
FIG. 1
depicts densely packed transistors arranged within and upon a test area of a substrate. Polysilicon gate conductors
12
,
14
, and
16
are spaced parallel to each other across a horizontal plane. Gate conductors
12
,
14
and
16
are laterally spaced relatively close to each other, e.g., less than 0.3 micron apart to form, e.g., a series-connected grouping of transistors. The test area and, specifically, the gate conductors
12
,
14
and
16
are used to replicate similar, series-connected transistors within the active die areas of the semiconductor wafer. Accordingly, source/drain regions
20
of the substrate which are each mutually shared by two transistors have relatively small lateral widths. Because source/drain regions
18
are not confined between closely spaced gate conductors, they have larger lateral widths than source/drain regions
20
. The small distance between gate conductors
12
and
14
and between gate conductors
14
and
16
afford high speed series-connected operation of, e.g., a multiple input logic device. Contacts would not normally be formed to source/drain regions
20
since an output would not ordinarily be present from regions
20
. Attempts to place contacts to source/drain regions
20
, e.g., for testing a single transistor of the series-connected transistor within the test area would be difficult at best.
Contact formation involves etching a contact opening, i.e., a via, through an interlevel dielectric, followed by filling the contact opening with a conductive material. A well-known technique known as “lithography” is used to pattern a photosensitive film, i.e., photoresist, above the interlevel dielectric to define the region to be etched. The portions of the interlevel dielectric to be removed are exposed while those portions to be retained are protected by the photoresist which remains intact during the etch step. The lateral width (i.e., the distance between opposed lateral edges) of the contact is thus mandated by the minimum lateral dimension that can be achieved for lithographically patterned features. Unfortunately, the minimum lateral dimension that can be defined using lithography is limited by, inter alia, the resolution of the optical system (i.e., aligner or printer) used to project an image onto the photoresist. The term “resolution” describes the ability of an optical system to distinguish closely spaced objects. Therefore, the lateral width of a contact formed to one of the source/drain regions
20
could not be less than the lateral distance between adjacent gate conductors, particularly since the distance between gate conductors is also dictated by lithography.
Perfect alignment of a photoresist pattern to the targeted features of a semiconductor substrate is rarely achievable. Thus, it is highly probable that the photoresist pattern used to define the region of the interlevel dielectric to be etched would be misaligned, resulting in contacts being shifted laterally from their targeted positions. If contacts were to be formed to source/drain regions
20
, portions of at least two of the gate conductors
12
,
14
, and
16
most likely would be undesirably etched. Consequently, the original lateral width of each gate conductor would be reduced, and the etched gate conductors would no longer be positioned immediately adjacent one of the source/drain regions
20
. Further, conductive material deposited into the contact openings would undesirably communicate with the etched gate conductors. An electrical short could thus be formed between the etched gate conductors and adjacent source/drain regions
20
, rendering the transistors inoperable. Alternately, the contacts could only be electrically linked to the etched gate conductors, making it impossible to pass electrical signals to and receive electrical signals from source/drain regions
20
for the purpose of testing a single transistor within the series-connected chain. The distinct properties of each of the transistors employing source/drain regions
20
thus could not be determined. Forming contacts to source/drain regions
20
in order to determine the characteristics of the transistors would in effect make it impossible to determine the properties of the devices in their original configuration. Therefore, forming contacts to source/drain regions
20
would defeat the purpose of creating the contacts in the first place.
To avoid the problems incurred when forming contacts to source/drain regions aligned between closely spaced gate conductors, conventional methods have turned to other means for electrically testing the device properties. As shown in
FIG. 1
, contacts
22
may be formed to source/drain regions
18
without damaging adjacent gate conductors
12
and
16
since regions
18
are not bound between closely-spaced gate conductors. Source/drain regions
18
are larger in lateral dimension than the minimum lateral dimension of lithographically patterned features. Accordingly, the lateral width of each contact may be reduced significantly below that of each source/drain region
18
. Thus, even if the photoresist pattern used to define the contacts is mis-aligned, some space in which the contacts may be formed still exists between the targeted contact positions and the gate conductors. Consequently, contact openings may be etched through a dielectric to source/drain regions
18
without risking the removal of portions of gate conductors
12
,
14
, and
16
. Contacts
22
may be electrically linked to probe pads
26
by horizon
Bush John J.
Cheek Jon D.
Fulford H. Jim
Advanced Micro Devices , Inc.
Conley & Rose & Tayon P.C.
Daffer Kevin L.
Hollington Jermele M.
Metjahic Safet
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