Test structure and methodology for characterizing etching in...

Details Test structure and methodology for characterizing etching in... Test structure and methodology for characterizing etching in...

1999-03-31

2001-07-10

Watkins, William P. (Department: 1772)

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C428S131000, C428S195100, C428S203000, C428S201000, C428S156000, C428S901000, C257S432000, C257S431000, C257S435000, C257S436000, C438S016000, C324S501000, C324S754120, C324S754120, C324S765010, C324S762010, C324S762010, C324S762010, C324S762010

Reexamination Certificate

active

06258437

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a test structure for characterizing integrated circuit etch processes.
2. Description of the Related Art
Fabricating integrated circuits involves placing numerous devices in a single semiconductor substrate and connecting isolated devices though specific electrical paths. Structures that electrically separate or “isolate” one device from another are thus required. Select devices may then be interconnected by conductors extending over a dielectric that isolates those devices. From this perspective, isolation and interconnect routing technologies are two of many critical aspects involved in fabricating a functional integrated circuit.
A popular isolation technology used in integrated circuits involves the technique known as “shallow trench isolation.” The shallow trench isolation process is better suited for isolating densely spaced active devices having field regions less than, e.g., 3.0-5.0 &mgr;m in the lateral dimension than is the previously developed local oxidation of silicon (“LOCOS”) technique. The trench isolation process involves etching a silicon substrate surface to a relatively shallow depth (e.g., between about 0.2 and 0.5 &mgr;m) and then filling the shallow trench with a deposited dielectric (referred to henceforth as “trench dielectric”). Some trench isolation processes include an interim step of growing silicon dioxide on trench walls prior to the trench being filled. After the trench is filled, it is then planarized to complete the isolation structure.
In order to connect isolated devices, many integrated circuits purposefully circumvent the isolation structures by routing an interconnect line between devices over the isolation dielectric. This is known as “local interconnect.” The interconnect generally connects the source (or drain) region on one device to the source (or drain) region, or to the gate conductor, on another device. Many types of materials may be used to establish local interconnects. For example, local interconnects can be formed from (i) a single or double-doped polycrystalline silicon (“polysilicon”), (ii) a refractory metal silicide upon polysilicon, (iii) multi-layered refractory metal partially converted to silicide, or (iv) refractory metal deposited by physical vapor deposition (“PVD”) or chemical vapor deposition (“CVD”).
Local interconnects, when covered with a dielectric, allow global interconnects such as metal conductors to extend over the local interconnect and buried contacts. Thus, local interconnects afford an additional interconnect level, provided the added resistance of a local interconnect would not deleteriously affect circuit performance. For this reason, local interconnects are generally used for short interconnect runs relative to much longer metal conductors. Local interconnects are used primarily to interconnect gates and sources and drains in MOS circuits, and are prevalent in, for example, high-density VLSI logic and SRAMs. An SRAM cell layout can be substantially reduced when a local interconnect level and associated buried contacts are used.
FIGS. 1A and 1B
depict a partial top plan view and a partial cross-sectional view along line B of
FIG. 1A
, respectively, of an exemplary integrated circuit topography
10
employing a local interconnect
42
. A pair of MOSFET transistors
4
and
6
are arranged a lateral spaced distance apart upon and within a semiconductor substrate. Transistors
4
and
6
include respective conductive gate structures
20
and
30
interposed between respective source/drain regions
16
and
18
. The source/drain regions
16
and
18
are arranged within the substrate and are isolated from each other by field isolation regions
14
. Local interconnect
42
extends across the substrate and isolation regions from conductive gate structure
20
of transistor
4
to one source/drain region
18
of transistor
6
. The local interconnect
42
is oriented such that it does not pass over source/drain regions
16
and cause unwanted shorting between conductive gate structure
20
and source/drain regions
16
. Using a local interconnect to couple a gate of one transistor to a source/drain region of another transistor is prevalent in, for example, high density VLSI logic and SRAMs.
Conductive gate structures
20
/
30
include gate conductors
24
/
34
residing a spaced distance above substrate
12
. As shown in
FIG. 1B
, gate conductor
34
is spaced above substrate
12
by gate dielectric
32
. Spacers
26
/
36
are formed adjacent opposed sidewalls of gate conductors
24
/
34
and above lightly doped drain areas such as areas
18
a.
Metal silicides
28
/
38
are formed upon upper surfaces of the gate conductors and the source/drain areas (e.g., areas
18
b
). The gate conductors typically include polycrystalline silicon that is rendered conductive by implanting dopants therein. The gate conductors are formed by depositing polysilicon upon a substrate, followed by etching away select portions of the polysilicon to define the gate conductors.
In contrast, local interconnects can be formed using the so-called damascene process. That is, an interlevel dielectric (such as interlevel dielectric
40
) is deposited across the substrate and gate areas, and then trenches are etched through the interlevel dielectric to the underlying gate areas and/or silicided source/drain areas. A conductive material, e.g., tungsten, is deposited into the trenches to a level spaced above the upper surface of the interlevel dielectric. The surface of the conductive material may be removed to a level commensurate with the upper surface of the interlevel dielectric using, e.g., chemical-mechanical polishing. Ohmic contacts (not shown) may also be formed by etching through an interlevel dielectric above the surfaces of interlevel dielectric
40
and local interconnect
42
. Openings (i.e., vias) are etched through the interlevel dielectric to underlying structures and then filled with a conductive material. Generally, contacts are used to couple global interconnect to local interconnect, gate conductors, junctions, and other levels of global interconnect.
The trenches in which metal local interconnects are formed may be several thousands of angstroms deep. As such, the time required for etching the trenches may be substantial, particularly if a significant over-etch is included in the process to ensure complete etching of the trenches uniformly across the wafer. The potential thus exists for damage to the underlying substrate and/or isolation regions. In particular, the metal silicide that may be formed upon the active areas to improve electrical connections to the source and drain is typically more resistant to the etchants used to form the trenches than is the silicon dioxide of the isolation regions. As such, because a material discontinuity exists at the interface between the active areas and the isolation regions, such interfaces are particularly subject to attack during the etching processes. If significant etching occurs at such interfaces, local interconnect metal may be introduced into the resulting fissures. Consequently, electrical connection may be made between the heavily doped source/drain regions and the oppositely doped bulk substrate, as well as between the substrate at one transistor and the gate of the other transistor to which the interconnect is coupled, causing the integrated circuit to become grounded or shorted to substrate
12
.
FIG. 2A
depicts an expanded view of region
2
of
FIG. 1B
according to an embodiment in which etching at the active region/isolation region interface is minimal. As such, no conductive pathway is formed between the substrate and the transistors formed upon and within the substrate. As shown in
FIG. 2A
, local interconnect
42
includes a tungsten layer
42
b
formed upon a titanium underlayer
42
a.
Titanium layer
42
a
is formed between tungsten layer
42
b
and the underlying topography to facilitate adhesion of the tungsten to

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