Test signal generating circuit

Details Test signal generating circuit Test signal generating circuit

1987-02-05

1989-01-31

Fleming, Michael R.

Excavating

371 28, G06F 304

Patent

active

048021687

ABSTRACT:
A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.

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patent: 4710932 (1987-12-01), Hiroshi
patent: 4719375 (1988-01-01), Martin

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