Excavating
Patent
1987-02-05
1989-01-31
Fleming, Michael R.
Excavating
371 28, G06F 304
Patent
active
048021687
ABSTRACT:
A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.
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Dehara Masayoshi
Yamanoi Koyu
Yoshizakiya Yoshio
Ando Electric Co. Ltd.
Fleming Michael R.
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