Excavating
Patent
1996-03-08
1999-05-11
Beausoliel, Jr., Robert W.
Excavating
39518306, G01R31/28
Patent
active
059035781
ABSTRACT:
A reduced netlist representing only partial netlist information for a logic block such as an ASIC embedded core is generated, such that proprietary information contained within the netlist can be kept confidential. The core is conceptually divided into a first section that can be completely tested using only a serial scan port, and a second section that can be tested in isolation from the first section using both primary inputs to the core as well as scan inputs. Netlist information for the first section is removed from the netlist, and the customer is supplied with serial scan test vectors that test the first section. Additionally, a multiplexing circuit selects either a serial scan chain for the entire logic block, or a scan chain that does not include scan cells within the first section of the logic bloc.
REFERENCES:
patent: 5291495 (1994-03-01), Udell, Jr.
patent: 5331570 (1994-07-01), Bershteyn
patent: 5502731 (1996-03-01), Meltzer
patent: 5519713 (1996-05-01), Baeg et al.
patent: 5528604 (1996-06-01), El-Maleh et al.
patent: 5534774 (1996-07-01), Moore et al.
patent: 5544173 (1996-08-01), Meltzer
International Test Conference 1991, Paper 14-2, Hierarchical Test Program Development for Scan Testable Circuits, pp. 375-384.
De Kaushik
Gunda Arun
Venkatraman Siva
Beausoliel, Jr. Robert W.
Iqbal Nadeem
LSI Logic Corporation
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