Boots – shoes – and leggings
Patent
1995-01-17
1997-05-20
Teska, Kevin J.
Boots, shoes, and leggings
324758, G01R 1512
Patent
active
056318561
ABSTRACT:
The sequential order of movements of a number of probes within a circuit test fixture is optimized through the use of an algorithm which sequentially orders test configurations provided in an input list. Each test configuration corresponds to the locations of probes within the fixture as a particular test is performed. In a first pass of the algorithm, for each test configuration, every other test configuration is considered as a next move candidate for which a weighted distance is calculated from the test configuration. Weighting factors reflect the degree of difficulty in moving one direction instead of another. A need to move one probe before another or to move in one direction before another, in order to prevent a collision within the test fixture, is also considered. A predetermined number of next move candidates having the lowest weighted distances are placed in an intermediate list for the test configuration. In a second pass of the algorithm, test configurations are linked, one to another, to form a list reflecting a preferred order of probe movement. In the process of linking with a test configuration, the available next move candidate having the shortest weighted distance is chosen from the intermediate list of the test configuration. If no available next move candidates remain in the intermediate list, the process returns to the first pass of the algorithm to get more next move candidates. Additionally, the algorithm is used to sequentially order individual points for a test fixture having only a single probe.
REFERENCES:
patent: 4565966 (1986-01-01), Burr et al.
patent: 5023557 (1991-06-01), Moran et al.
patent: 5155679 (1992-10-01), Jain et al.
patent: 5214746 (1993-05-01), Fogel et al.
patent: 5222192 (1993-06-01), Shaefer
patent: 5272638 (1993-12-01), Martin et al.
patent: 5418953 (1995-05-01), Hunt et al.
patent: 5469064 (1995-11-01), Kerschner et al.
patent: 5485081 (1996-01-01), Whitehead et al.
patent: 5550483 (1996-08-01), Boyette, Jr. et al.
Keller Steven A.
Lo Jiann-Chang
Mahlbacher James C.
Davidge Ronald V.
International Business Machines - Corporation
Loppnow Matthew
Teska Kevin J.
Tomlin Richard A.
LandOfFree
Test sequence optimization process for a circuit tester does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Test sequence optimization process for a circuit tester, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Test sequence optimization process for a circuit tester will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1729129